Cypress Semiconductor STK11C68 사양 시트 - 페이지 10
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페이지 인쇄Software Controlled STORE/RECALL Cycle
The software controlled STORE/RECALL cycle follows.
Parameter
Alt
t
t
RC
AVAV
[10]
t
t
SA
AVEL
[10]
t
t
CW
ELEH
[10]
t
t
HACE
ELAX
[10]
t
RECALL
Switching Waveform
ADDRESS
t
SA
CE
OE
DQ (DATA)
Notes
10. The software sequence is clocked on the falling edge of CE without involving OE (double clocking aborts the sequence).
11. The six consecutive addresses must be read in the order listed in
Document Number: 001-50638 Rev. **
[10, 11]
Description
STORE/RECALL Initiation Cycle Time
Address Setup Time
Clock Pulse Width
Address Hold Time
RECALL Duration
Figure 10. CE Controlled Software STORE/RECALL Cycle
t
RC
A
D
D
R
E
S
S
#
1
t
SCE
t
HACE
DATA VALID
Table 1
25 ns
Min
Max
25
0
20
20
20
t
RC
A
D
D
R
E
S
S
#
6
DATA VALID
on page 4. WE must be HIGH during all six consecutive cycles.
STK11C68
35 ns
45 ns
Min
Max
Min
Max
35
45
0
0
25
30
20
20
20
20
[11]
t
/ t
STORE
RECALL
HIGH IMPEDANCE
Page 10 of 16
Unit
ns
ns
ns
ns
μs
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