Bose Lifestyle 28 Troubleshooting Manual - Page 29

Browse online or download pdf Troubleshooting Manual for Amplifier Bose Lifestyle 28. Bose Lifestyle 28 32 pages. Dvd home entertainment systems
Also for Bose Lifestyle 28: Installation Manual (32 pages), Operating Manual (44 pages), Owner's Manual (22 pages), Operating Manual (46 pages), Operating Manual (44 pages), Operating Manual (34 pages)

Print Page
Bose Lifestyle 28 Troubleshooting Manual
Pin
Type
BSEL
I
EPROM Boot Select. When BSEL is high, the ADSP-21065L is configured for
booting from 8-bit EPROM. When BSEL is low, the BSEL and BMS inputs
determine booting mode. See BMS for details. This signal is a system
configuration selection which should be hardwired.
____
I/O/T*
Boot Memory Select. Output Used as chip select for boot EPROM devices (when
BMS
BSEL = 1). In a multiprocessor system, BMS is output by the bus master. Input:
When low, indicates that no booting will occur and that ADSP-21065L will begin
executing instructions from external memory. See table below. This input is a
system configuration selection which should be hardwired. *Three-statable only in
EPROM boot mode (when BMS is an output).
BSEL
I
0
0
CLKIN
I
Clock In. Used in conjuction with XTAL, configures the ADSP-21065L to use
either its internal clok generator or an external clock source. The external crystal
should be rated at 1x frequency. Connecting necessary components to CLKIN and
XTAL enables the internal clock generator. The ADSP-21065L's internal clock
generator multiplies the 1x clock to generate 2x clock for its core and SDRAM. It
drives 2x clock out on the SDCLKx pins for SDRAM interface to use. See also
SDCLKx Connecting the 1x external clock to CLKIN while leaving XTAL
unconnected configures configures the ADSP-21065L to use the external clock
source. The instruction cycle rate is 2x CLKIN. CLKIN may not be halted, changed.
or operated below the specified frequency.
Processor Reset. Resets the ADSP-21065L to a known state and begins
______
I/A
RESET
execution at the program memory location specified by the hardware reset vector
address. This input must be asserted (low) at power-up.
TCK
I
Test Clock (JTAG). Provides an asynchronous clock for JTAG boundary scan.
Test Mode Select JTAG). Used to control the test state machine. TMS has a 20 k
TMS
I/S
internal pull-up resistor.
TDI
I/S
Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has
a 20 k internal pull-up resistor.
TDO
O
Test Data Output (JTAG). Serial scan output of the boundary scan path.
_____
I/A
Test Reset (JTAG). Resets the test state machine. TRST must be asserted
TRST
(pulsed low) after power-up or held low for proper operation of the ADSP-21065L.
TRST has a 20 k internal pull-up resistor.
____
O
Emulation Status. Must be connected to the ADSP-21065L EZ-ICE target board
EMU (O/D)
connector only.
BMSTR
O
Bus Master Output. In a multi pprocessor system, indicates whether the asserted
ADSP-21065L is current bus master of the shared external bus. The ADSP-
21065L drives the BMSTR high only while it is the bus master. In a single -
processsor system (ID- 00), the processor drives this pin high.
SDRAM Column Access Strobe. provides the column address. In conjunction
CAS
I/O/T
with RAS MSx, SDWE, SDCLK and sometimes SDA10, defines the operation for
the SDRAM to perform.
____
I/O/T
SDRAM Row Access Strobe. provides the column address. In conjunction with
RAS
CAS MSx, SDWE, SDCLK and sometimes SDA10, defines the operation for the
SDRAM to perform.
Integrated Circuit Diagrams
DSP ADSP21065LKS
part number 254191-001
BMS
Output
1 (Input)
0 (Input)
29
PS18/28/35 Troubleshooting Guide
Function
Booting Mode
EPROM (Connect BMS
to EPROM chip select.)
Host Processor (HBW
[SYSCON] bit select host
bus width).
No Booting. Processor
executes from external
memory.