CEL THine THC63LVDM83D Manual - Page 2

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CEL THine THC63LVDM83D Manual
THAN0184_Rev.1. 0_E
THC63LVDM83D / THC63LVDF(R)84C Evaluation Kit
1.General Description
THEVAM83D and, THEVAF(R)84C boards are
designed to support video data transmission
between the host and display. One high-speed lane
can carry up to 24bits data and 3bits of
synchronizing signals at a pixel clock frequency
from 8MHz to 160MHz.
Table 1 Clock Frequency
Type
Parts Number
Tx
THEVAM83D
Rx
THEVAF(R)84C
3. Overview
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LVDS Single Link Evaluation Board
Parts Number: THEVAM83D, THEVAF(R)84C
TTL Clock Freq.
8MHz to 160MHz
8MHz to 112MHz
(a) THEVAM83D (Top Side)
Figure 1 THEVAM83D and THEVAF(R)84C Top Side View
(a) THEVAM83D (Bottom Side)
Figure 2 THEVAM83D and THEVAF(R)84C Bottom Side View
2. Features
Compatible with TIA/EIA-644 LVDS Standard
7:1 LVDS Transmitter and Receiver
Single power supply
Power Down Mode
< THEVAM83D>
LVDS swing is reducible as 200mV by RS-pin
to reduce EMI and power consumption.
Input clock triggering edge is selectable by
R/F-pin
< THEVAF84C> Falling Edge Clock
< THEVAR84C> Rising Edge Clock
(b) THEVAF(R)84C (Top Side)
(b)THEVAF(R)84C (Bottom Side)
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