Broadcom ACPL-337J Reference Manual - Page 9

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Broadcom ACPL-337J Reference Manual
ACPL-337J Reference Manual
Fuji Electric PIM Module EP2 Package Evaluation Board
The ACPL-337J has an integrated input LED driver with high impedance input (VIN+) for interfacing with the controller. The
LED driver's output (VLEDDRV) must be connected with the recommended split resistors to LED1 to achieve the rated high
CMR performance of more than 50kV/µs. If the LED driver is not used, LED1 can still be driven directly by other means of
discrete driver configuration.
It is recommended that the two resistors (R4/R5) connected to input LED's anode and cathode are split in the ratio 1:1. They
will help to balance the common mode impedances at the LED's anode and cathode. This helps to equalize the common
mode voltage changes at the anode and cathode to give high CMR performance. In this case, R4 and R5 are 150Ω resistors
to limit LED1 current to about 10 mA based on 5V VCC1 supply.
The primary side has two open drain FAULT and UVLO feedback outputs suitable for wired 'OR' applications. ACPL-337J
monitors the output power supply constantly. When secondary side power supply is lower than undervoltage lockout (UVLO)
threshold, the gate driver output will shut off to protect IGBT from low voltage bias. The low output power supply fault will be
reported through the UVLO feedback. In this way, the UVLO feedback can also serve as a READY signal to the controller
during power up. These open drain FAULT and UVLO outputs are connected to 10kΩ pull-up resistors (R2/R3) and 330 pF
filtering capacitors (C6/C7).
The supplies, VCC1 and VCC2 are connected to C5, C113, C115, and C117 (1 µF) bypass decoupling capacitors to provide
the large transient currents necessary during a switching transition.
The ACPL-337J monitors the saturation (collector) voltage of the IGBT and triggers a local shutdown sequence if the
collector voltage exceeds a predetermined threshold of 7V during short circuit or over current fault condition. The DESAT
pin is connected to the collector of IGBT (P1) via 600V high voltage blocking diodes, D101, D102, and resistor R105 (1kΩ).
Blanking capacitor, C114 (220 pF) is used to prevent false fault detection by filtering high frequency noise transient.
The VCLAMP pin is connected directly to the gate of the IGBT and can sink 3A of parasitic Miller current during switching to
prevent false turn on of the IGBT.
The gate resistors R108 (15Ω) and R107 (0Ω) serve to limit gate current and indirectly control the IGBT switching time.
Diode, D105, is used to bypass resistor R107 and control the gate current and slew rate during IGBT gate discharging. It
should be noted that the gate resistor must limit ACPL-337J peak output current to within 4A absolute maximum.
Broadcom
ACPL-337J-EP2-RM100
9