Fujitsu CPU369-Module Documentation - Page 7

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3.2 Operating Mode (SW2)
SW2
Boot signal (SW2/1)
MD2 (SW2/2)
MD1 (SW2/3)
MD0 (SW2/4)
3.3 UART (JP21, JP22)
SOT_0
(JP21)
SIN_0
(JP22)
Reserved future extension:
SIN_2
(JP7)
SOT_2
(JP8)
UART2 clock
(JP9)
3.4 Chip select enable for FLASH (JP10)
CS
CS2
CS3
DIP switch
Logical value
setting
ON
ON
ON
ON
Jumper setting
ON (closed)
UART0 Output enable
OFF (open)
UART0 Output disable
Jumper setting
ON (closed)
OFF (open)
UART0 Input disable
Description
UART2 Input enable
Description
UART2 Output enable
Description
UART2 clock enable
Jumper setting
ON (closed 1-2)
Ext. Flash – Chip-Select2
ON (closed 2-3)
Ext. Flash – Chip-Select 3
0 (low)
0 (low)
0 (low)
0 (low)
Description
Description
UART0 Input enable
Description
Description
Boot signal
Internal ROM mode
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