Fujitsu MB91460 SERIES Application Note - Page 12

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2.5.1.2 Condition Code Register (CCR)

The CCR consists of the following bits:

Bit

Initial

No.

Name

Value

Interrupts can be enabled globally by the C language extension __EI() and disabled by

__DI().

There is no direct bit access to the CCR in assembler, but bits can be set indirectly with

logical instructions: Setting the I-Bit: ORCCR #10 and clearing it: ANDCCR #EF.

Please note, that __DI() and __EI() cannot be set consecutively. Please set at least one

instruction in-between, such as a NOP.

Wrong

__DI();

__EI();

__DI();

2.5.1.3 System Condition Code Register (SCR)

The SCR consists of the following bits:

Bit

Initial

No.

Name

Value

MCU-AN-300055-E-V10

INTERRUPTS

Chapter 2 Interrupt Types

Description

Supervisor Mode Flag.

1 = User Mode, 0 = Supervisor Mode

System/User Stack Flag. 0 = System Stack, 1 = User Stack.

This bit is set to "1" after in case of all EITs

Global Interrupt Enable Flag

Negative Flag

Zero Flag

Overflow Flag

Carry Flag

Table 2-5: Condition Code Register

__DI();

__wait_nop;

__EI();

__wait_nop();

__DI();

Description

Step Division Flag.

These bits hold intermediate data during the execution of step

division.

Step Trace Trap Flag.

Setting this bit enables step trace trap. Its used by the emulator.

Table 2-6: System Condition Code Register

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Correct