Dell 3250 Product Manual - Page 27

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Intel® Server Platform SR870BH2

8.3.2

Late Self-test Usage Notes

Because the late self-test relies on encapsulated PAL code, there are certain conditions under

which the test will operate. These are listed below.

Only one processor will be disabled per boot cycle.

On the next boot, the unhealthy processor is not included in the system boot.

If errors occur during any processor late self-test, the POST error manager will not be

displayed on the boot cycle in which the error is detected.

The POST error manager will only display the fact that a processor is disabled and this

will occur on the boot cycle after the processor is disabled. In order to determine if the

processor is disabled because of late self-test errors, the SEL will have to be referenced.

8.4

The BIOS Setup offers a control item that allows the OS load watchdog timer to be enabled or

disabled. The default for the OS load watchdog timer function is disabled. The server BIOS will

support the OS load watchdog timer. This may also be referred to as FRB-4, although the term

"OS load watchdog timer" is more accurate, as this timer has no FRB-related connection to

disabling processors.

8.4.1

The Watchdog Timer can be enabled / modified in system setup (Enter Setup / startup options)

this menu item is also located under the System Management Submenu – Platform Event

Filters (PEF). The watchdog timer provides a 'timer use' field that indicates the current use

assigned to the watchdog timer. If enabled and depending on selections configured the timer

allows the user to:

Log an event to SEL upon expiration of the OS load watchdog timer.

Select the timeout action to be hard reset, and pre-timeout interrupt type to none.

Set the pre-timeout interval to zero; the pre-timeout action occurs concurrently with the

timeout action.

Program the countdown value to selectable seconds.

8.4.2

In most cases this issue is caused by the boot device time out, bad / missing boot block or a

corrupted file or file system which causes the system to loop or wait and the timer to trigger

(approx. 6 minutes). Depending on boot device / method, the Hard disk subsystem and related

component should be reviewed and tested.

8.5

The BIOS and BMC firmware provide a feature to guarantee that the system boots, even if one

or more processors fails during POST. The BMC contains two FRB timers that can be

configured to reset the system upon time out.

Revision 1.1

Debug Methodology and Failure Isolation