Dell
7 Memory
7.1 Overview
The M610xD utilizes DDR3 memory providing a high-performance, high-speed memory interface
capable of low latency response and high throughput. The M610x supports Registered ECC DDR3
DIMMs (RDIMM) as well as the low-voltage RDIMMs and Unbuffered ECC DDR3 DIMMs (UDIMM).
The DDR3 memory interface consists of three channels, with up to two RDIMMs or UDIMMs per
channel for single/dual rank and up to two RDIMMs per channel for quad rank. The interface uses 2
GB, 4 GB, or 8 GB RDIMMs. 1 GB or 2 GB UDIMMs are also supported. The memory mode is dependent
on how the memory is populated in the system:
Three channels per CPU populated identically
o Typically, the system will be set to run in Memory Optimized (Independent Channel) mode in
this configuration. This mode offers the most DIMM population flexibility and system memory
capacity, but offers the least number of RAS (reliability, availability, and serviceability)
features.
o All three channels must be populated identically.
o Memory sparing is not supported on the M610x with 5500 series processors.
The first two channels per CPU populated identically with the third channel unused
o Typically, two channels operate in Advanced ECC (Lockstep) mode with each other by having
the cache line split across both channels. This mode provides improved RAS features (SDDC
support for x8-based memory).
o For Memory Mirroring, two channels operate as mirrors of each other—write functions go to
both channels and read functions alternate between the two channels.
One channel per CPU populated (This is a simple Memory Optimized mode. No mirroring or
sparing is supported.)
The M610x memory interface supports memory demand and patrol scrubbing, single-bit correction,
and multi-bit error detection. Correction of a x4 or x8 device failure is also possible with SDDC in the
Advanced ECC mode. Additionally, correction of a x4 device failure is possible in the Memory
Optimized mode.
7.2 DIMMs Supported
The following memory requirements apply to the M610x:
If DIMMs of different speeds are mixed, all channels operate at the fastest common
frequency.
RDIMMs and UDIMMs cannot be mixed.
If memory mirroring is enabled, identical DIMMs must be installed in the same slots across
both channels. The third channel of each processor is unavailable for memory mirroring.
The first DIMM slot in each channel is color-coded with white ejection tabs for ease of
installation.
The M610x memory system supports up to 12 DIMMs. DIMMs must be installed in each channel
starting with the DIMM farthest from the processor. Population order will be identified by the
silkscreen designator and the System Information Label (SIL) located on the chassis cover.
Dell PowerEdge M610x Technical Guide
17
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