Chrontel CH7219 Application Note - Page 5

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CHRONTEL
2.5
Display Port Signal Pins
• DP0P/N, DP1P/N, DP2P/N, DP3P/N
These pins accept two AC-coupled differential pair signals from the Display Port transmitter or the Type-C DP Alt.
For USB Type-C Receptacle application, DP Main link lane swap is supported for compliance with the USB type C
cable plug orientation switch.
Since the digital serial data of the CH7219 may be toggled at speeds up to 8.1 Gbps, it is strongly recommended that
the connection of these video signals between the graphics controller and the CH7219 be kept as short as possible,
avoid discontinuities in the reference plane and be isolated as much as possible from the analog outputs and analog
circuitry. For optimal performance, these signals should not overlay the analog power or analog output signals. When
a signal pair has to changes layers, the ground stitching vias should be placed close to the signal vias. A minimum of
1 to 3 stitching vias per pair of signals is recommended. Never route a trace so that it straddles a plane split. It is
recommended that 5 mils traces be used in routing these signals. There should be 7 mils spacing between each intra
pair. The length for a pair of intra differential signals should be matched within 5 mils. The length for inter pairs
should be matched within 50mils. Bend smaller than 45 degrees should be avoided. The AC coupling capacitors for
the serial video inputs must be placed close to the GMCH, as shown in Figure 7.
CH7219
Figure 7: CH7219 DP Main Link Lane or USB Type-C DP Alt Mode Inputs
• AUXP and AUXN
These two pins are for Display Port AUX channel control or USB Type-C DP Alt Mode that accepts a half-duplex,
bi-directional AC-coupled differential signal. An AC coupling capacitor, 0.1μF recommended, must be placed on the
end as shown in Figure 8.
• HPD_DP
This output pin indicates whether the device is active or not. It also generates an interrupt pulse as defined by the
Display Port standard. Output voltage is 3.3V. A resistor, greater than 100KΩ, should be connected between this pin
and GND as shown in Figure 8.
206-1000-058
Rev. 0.1
C1
56
D0P
57
C2
D0N
C3
60
D1P
61
CH7219
C4
D1N
63
C5
D2P
64
C6
D2N
67
C7
D3P
68
C8
D3N
56
D0P
57
D0N
60
D1P
61
D1N
63
D2P
64
D2N
67
D3P
68
D3N
2023-10-25
100nF
D0P
100nF
D0N
100nF
D1P
100nF
D1N
GMCH
100nF
D2P
100nF
D2N
100nF
D3P
100nF
D3N
DP Source
C10 100nF
B3
ML0-
B2
C12 100nF
ML0+
C14 100nF
A2
ML3+
C16 100nF
A3
ML3-
C18 100nF
B11
ML2+
B10
C20 100nF
ML2-
A10
C22
100nF
ML1-
A11
100nF
C24
ML1+
Type-C Connector
UFP_D Pin Assignment C
AN-B058
5