Chrontel CH7515A Layout Design Manual - Page 5

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CHRONTEL
JP1
SPC0
2
HEADER 1x2
VCC3_3
R3
R4
6.8K
6.8K
Note:
1. Pease make sure the Voltage (3.3V) should be given earlier than the DVDD and VDDPLL.
2. If the SPC0/SPD0 or AUX channel is used to update the CH9904, the precondition is that MCU firmware
must work well. We advise that the customers use IIC/SMBUS to update CH9904 by linking IIC/SMBUS to
SPC0 and SPD0
2.5
Display Port Signal Pins
• RXP/N0, RXP/N1, RXP/N2, RXP/N3
These pins accept four AC-coupled differential pair signals from the Display Port transmitter.
Since the digital serial data of the CH7515A may be toggled at speeds up to 2.7 GHz, it is strongly recommended that
the connection of these video signals between the graphics controller and the CH7515A should be kept as short as
possible and be isolated as much as possible from the analog outputs and analog circuitry. For optimum performance,
these signals should not overlay the analog power or analog output signals. It is recommended that 5 mils traces
should be used in routing these signals. There should be 7 mils spacing between each intra pair. The length for a pair
of intra differential signals should be matched within 5 mils. The length for inter pairs should be matched within
10mils. Bend, which is smaller than 45 degrees should be avoided. The AC coupling capacitors for the serial video
inputs must be placed close to the GMCH, as shown in Figure 5
.
206-1000-021
Rev 1.0
JP2
SPC1
SPD0
1
2
HEADER 1x2
VCC3_3
R5
6.8K
U2
1
8
GP1
VCC
2
7
R8 10K
GP2
WE
3
6
GP3
SPC
4
5
GND
SPD
CH9904
Boot Rom
Figure 4: Serial Port Control
U1
124
RXN3
123
RXP3
121
RXN2
120
RXP2
118
RXN1
117
RXP1
115
RXN0
114
RXP0
CH7515A
Figure 5: CH7515A DispalyPort Main Link Lane Inputs
2020-07-15
VCC3_3
SPD1
1
2
2
R1
R2
VCC3_3
6.8K
6.8K
1
1
SPC0
2
2
R6
R7
SPD0
6.8K
6.8K
1
1
SPC1
SPD1
1
C1
0.1uF
2
C1
0.1uF
RXN3
C2
0.1uF
RXP3
C3
0.1uF
RXN2
C4
0.1uF
RXP2
C5
0.1uF
RXN1
C6
0.1uF
RXP1
C7
0.1uF
RXN0
C8
0.1uF
RXP0
Soure
AN-B021
U1
107
SPC0
106
SPD0
105
SPC1
104
SPD1
CH7515A
U2
GMCH
5