Alpha Data ADM-SDEV-CFG1 User Manual - Page 5
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V1.2 - 18th March 2020
1 Introduction
The ADM-SDEV-CFG1 configuration module board forms part of the ADA-SDEV-KIT1 space FPGA
development kit.
The ADM-SDEV-CFG1 board connects to the configuration FMC socket of the ADM-SDEV-BASE board, allowing
the Xilinx tools to interrogate and configure its FPGA.
1.1 Key Features
Key Features
•
1x FMC form factor configuration interface
•
2x 256MB QSPI Flash devices, connected to the configuration bank of the Base board FPGA
•
IPASS Connector, allowing remote PCIe connection to the Base board FPGA
•
A JTAG header to allow Vivado Hardware Manager configuration and debug
•
USB connection to the Base boards system monitor, to allow reporting of system monitor values
•
2x SATA sockets, allows access to 2 high speed serial lanes of the Base board FPGA.
•
Fixed LVDS clock output to the Base board FPGA.
•
2x UFL connectors, allows an external clock to be transmitted / received / looped back by the Base board
FPGA.
•
GPIO loopbacks on the remaining FMC signals.
Introduction
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Figure 1 : ADM-SDEV-CFG1 Top and Bottom Views
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