Motorola CP040 Service Information - Page 11

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Motorola CP040 Service Information
Controller Circuits
3.2.9
Microprocessor 7.3975 MHz Clock
The 7.3975 MHz clock signal (uP_CLK) is provided from the ASFIC_CMP (U451 pin 28). Upon
startup the 16.8MHz crystal provides the signal to the ASFIC_CMP, which sends out the uP_CLK at
3.8MHz until a steady-state condition is reached and the clock is increased to 7.3975MHz for the
microprocessor.
3.2.10
Battery Gauge
Various battery types are available having different capacities. The different battery types contain
internal resistors connected from the BATT_CHARGE contact to ground (which is routed to the
microprocessor as BATT_DETECT). A voltage divider is formed with R255 producing a different DC
voltage for each battery type, which is read by microprocessor port PE2 (pin 65). This allows the
software to recognize the battery chemistry being used and adjust the battery gauge for best
accuracy.
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