Motorola GP320 Series Service Information - Page 6
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1-2
3.0
Controller Circuits
3.1
Controller Architecture
The controller board is the central interface between the various subsystems of the radio. It is
separated into MCU digital and audio/signalling architectures as shown in Figure 1-2.
16.8 MHz
Reference Clock
from Synthesizer
Recovered Audio
Squelch
To RF Board
3.2
MCU Digital Architecture
( Refer to Figure 1-2, the Microprocessor and the Memory schematic diagrams )
The digital architecture portion consists of a microcontroller and associated EEPROM, RAM, and
ROM memories. The architecture is commonly used for both low-tier and high-tier products and also
includes conventional and trunking portables. Combinations of different size RAM and ROM are
available to support various application software. RAM supports 8KB and 32KB sizes. ROM
supports 128KB, 256KB, and 512KB sizes. Table 1-1 shows the ROM, RAM and EEPROM
requirements for different applications.
To Synthesizer
Mod
Out
ASFIC_CMP
3.3V
Regulator
(Vdda)
SPI
MCU Digital
Architecture
3.3V
Regulator
(Vddd)
Figure 1-2 Controller Block Diagram
Audio/Signalling
Architecture
Audio Power
Amplifier/Filter
µP Clock
Microcontroller
EEPROM
RAM
ROM
THEORY OF OPERATION
External
Microphone
Internal
Microphone
External
Speaker
Internal
Speaker
SCI to Side
Connector