Pioneer AVD-505 Service Manual - Page 27
Browse online or download pdf Service Manual for Monitor Pioneer AVD-505. Pioneer AVD-505 32 pages. Color display
Print Page- Pin Functions (LZ9GF16)
Pin No.
Pin Name
1
VIN
2
CVOP
3
CVIN
4
DVOP
5
FRPT
6
GPS
7
GND
8
EXCL
9
SYNI
hsy
10
vsy
11
12
DIS
13
TESTO
14
NTPC
15
VRVC
16
HRVC
17
CHK
18
TESTI
19
TESTO
20
VR
21
SPS
22
CLS
23
LOWO
24
CTR
25
SPD
26
CLD
27
OSCO
28
OSCI
29
SAMO
30
VDD
31
GND
32
TESTI
33
LOWI
34
FRPV
35
RESH
36
PDP
37
RESV
38,39
TESTI
40
IHR
41
HR
42
CLOC
43
CLKC
44
TESTI
45
SAMC
46
BLKI
47
BLKO
48
SYNO
I/O
Function and Operation
I
Vertical synchronizing signal input (positive electrode)
O
Vertical synchronizing countdown output
I
Vertical synchronizing countdown input
O
Digital separation vertically synchronized output (positive electrode)
O
Signal output for common electrode drive signal polarity inversion
O
Signal output for gate power supply
Power supply ground
I/O
Clock signal input/output
I
Composite synchronizing signal input
I/O
Horizontal synchronizing signal input/output (negative electrode)
I/O
Vertical synchronizing signal input/output (negative electrode)
O
Source driver control signal output
O
Test monitor signal output
I
Terminal for setting NTSC/PAL
I
Terminal for setting vertical scanning direction
I
Terminal for setting horizontal scanning direction
O
Control signal output for backlight PWM Light adjuster
I
Input terminal for testing
O
Test monitor signal output
O
Vertical scanning direction setting output for gate driver
O
Gate driver start signal output
O
Gate driver clock signal output
O
Gate driver control signal output
O
Source driver control signal output
O
Source driver start signal output
O
Source driver clock signal output
O
Clock oscillation circuit output
I/O
Clock oscillation circuit input/output
O
Source driver control signal output
Power supply (+5V)
Power supply ground
I
Input terminal for testing
I
Initial reset signal input
O
Signal output for video signal polarity inversion
I
Signal output reset terminal for source driver
O
PLL Phase comparison circuit output
I
Signal output reset terminal for gate driver
I
Input terminal for testing
O
Source driver control signal output
O
Source driver control signal output
I
Terminal for setting EXCL (clock signal) output
H:L-Level output L:Clock output
I
Terminal for setting clock · synchronizing signal input/output
H:EXCL · hsy · vsy signal output L:EXCL · hsy · vsy signal input
I
Input terminal for testing
I
Terminal for setting sampling mode
H:Non-simultaneous sampling
I
PLL phase comparison input
O
Output for PLL phase comparison signal
O
Composite synchronizing signal output for vertical synchronized
separation (positive electrode)
H:NTSC
L:MBK-PAL
H:Normal
H:Normal
H:Normal
H:Normal
L:Simultaneous sampling
Input BLKO delayed signal
Input into BLKI following delay
AVD-505
L:Reverse
L:Reverse
L:Forced reset
L:Forced reset
27