AcQuisition Technology Quad M-module Carrier i4000 Hardware Manual - Page 17

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5.2.4.

Vector registers

Each module interrupt input has its own associated vector register. Each register is 8 bits
wide and supplies a data byte during its interrupt acknowledge cycle if the associated
External/Internal (X/IN*) control register bit is clear (zero). This data can be status,
identification, or address information depending on system usage. The information is
programmed by the system user.
5.2.5.

Interrupt controller reset

When a VMEbus reset is applied, the control registers of the i4000 interrupt controller
are set to all zeros (low). The vector registers however are uninitialized and should be
programmed before use.
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