Cypress CY62136VN Specification Sheet

Browse online or download pdf Specification Sheet for Computer Hardware Cypress CY62136VN. Cypress CY62136VN 13 pages. Mobl 2-mbit (128k x 16) static ram

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Features
• Temperature Ranges
— Industrial: –40°C to 85°C
— Automotive-A: –40°C to 85°C
— Automotive-E: –40°C to 125°C
• High speed: 55 ns
• Wide voltage range: 2.7V–3.6V
• Ultra-low active, standby power
• Easy memory expansion with CE and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Available in standard Pb-free 44-pin TSOP Type II,
Pb-free and non Pb-free 48-ball FBGA packages
Functional Description
The CY62136VN is a high-performance CMOS static RAM
organized as 128K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™ (MoBL
Logic Block Diagram
DATA IN DRIVERS
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
COLUMN DECODER
Note:
1. For best practice recommendations, please refer to the Cypress application note "System Design Guidelines" on http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 001-06510 Rev. *A
[1]
®
) in
128K x 16
RAM Array
•
198 Champion Court
CY62136VN MoBL
2-Mbit (128K x 16) Static RAM
portable applications such as cellular telephones. The device
also has an automatic power-down feature that significantly
reduces power consumption by 99% when addresses are not
toggling. The device can also be put into standby mode when
deselected (CE HIGH). The input/output pins (I/O
I/O
) are placed in a high-impedance state when: deselected
15
(CE HIGH), outputs are disabled (OE HIGH), BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
written into the location specified on the address pins (A
through A
). If Byte High Enable (BHE) is LOW, then data
16
from I/O pins (I/O
through I/O
8
specified on the address pins (A
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
to I/O
0
LOW, then data from memory will appear on I/O
the Truth Table at the back of this data sheet for a complete
description of read and write modes.
Pin Configurations
A
A
A
A
A
CE
I/O
– I/O
I/O
0
7
I/O
I/O
– I/O
I/O
8
15
I/O
V
CC
V
SS
I/O
I/O
I/O
I/O
WE
A
BHE
A
WE
A
CE
A
OE
A
BLE
,
•
San Jose
CA 95134-1709
through
0
through I/O
), is
0
7
) is written into the location
15
through A
).
0
16
. If Byte High Enable (BHE) is
7
to I/O
. See
8
15
[3]
TSOP II (Forward)
Top View
44
A
1
4
5
A
43
2
3
6
3
42
A
2
7
OE
41
4
1
40
BHE
5
0
39
BLE
6
38
I/O
7
0
15
37
I/O
8
1
14
36
I/O
9
2
13
35
10
I/O
3
12
V
34
11
SS
33
V
12
CC
I/O
13
32
4
11
I/O
31
14
10
5
I/O
30
15
6
9
I/O
29
16
8
7
28
NC
17
A
18
27
8
16
19
A
26
15
9
A
20
25
14
10
A
21
24
13
11
NC
22
23
12
•
408-943-2600
Revised August 3, 2006
®
0
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