Cypress Semiconductor CY7C1231H Specification Sheet - Page 5

Browse online or download pdf Specification Sheet for Computer Hardware Cypress Semiconductor CY7C1231H. Cypress Semiconductor CY7C1231H 13 pages. Cypress 2-mbit (128k x 18) flow-through sram with nobl architecture specification sheet

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Linear Burst Address Table (MODE = GND)
First
Second
Address
Address
A1, A0
A1, A0
00
01
01
10
10
11
11
00
ZZ Mode Electrical Characteristics
Parameter
I
Sleep mode standby current
DDZZ
t
Device operation to ZZ
ZZS
t
ZZ recovery time
ZZREC
t
ZZ Active to sleep current
ZZI
t
ZZ inactive to exit sleep current
RZZI
[2, 3, 4, 5, 6, 7, 8]
Truth Table
Operation
Deselect Cycle
Deselect Cycle
Deselect Cycle
Continue Deselect Cycle
READ Cycle (Begin Burst)
READ Cycle (Continue Burst)
NOP/DUMMY READ (Begin Burst)
DUMMY READ (Continue Burst)
WRITE Cycle (Begin Burst)
WRITE Cycle (Continue Burst)
NOP/WRITE ABORT (Begin Burst)
WRITE ABORT (Continue Burst)
IGNORE CLOCK EDGE (Stall)
Sleep MODE
Truth Table for Read/Write
Read
Write – No bytes written
Write Byte A – (DQ
and DQP
A
Write Byte B – (DQ
and DQP
B
Write All Bytes
Notes:
2. X = "Don't Care." H = Logic HIGH, L = Logic LOW. BWx = 0 signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired byte write
selects are asserted, see Truth Table for details.
3. Write is defined by BW
, and WE. See Truth Table for Read/Write.
[A:B]
4. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.
5. The DQs and DQP
pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
[A:B]
6. CEN = H, inserts wait states.
7. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP
OE is inactive or when the device is deselected, and DQs and DQP
Document #: 001-00207 Rev. *B
Third
Fourth
Address
Address
A1, A0
A1, A0
10
11
11
00
00
01
01
10
Description
ZZ > V
ZZ > V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
Address
Used
CE
CE2 CE
1
None
H
X
None
X
X
None
X
L
None
X
X
External
L
H
Next
X
X
External
L
H
Next
X
X
External
L
H
Next
X
X
None
L
H
Next
X
X
Current
X
X
None
X
X
[2, 3]
Function
)
A
)
B
= data when OE is active.
[A:B]
Interleaved Burst Sequence
First
Second
Address
Address
A1, A0
A1, A0
00
01
01
00
10
11
11
10
Test Conditions
− 0.2V
DD
− 0.2V
DD
ZZ ADV/LD WE BW
3
X
X
L
L
X
X
H
L
L
X
X
X
L
L
X
X
X
L
H
X
X
L
L
L
H
X
X
L
H
X
X
L
L
L
H
X
X
L
H
X
X
L
L
L
L
L
X
L
H
X
L
L
L
L
L
H
X
L
H
X
H
X
L
X
X
X
X
H
X
X
X
WE
H
L
L
L
L
CY7C1231H
Third
Fourth
Address
Address
A1, A0
A1, A0
10
11
11
10
00
01
01
00
Min.
Max.
Unit
40
mA
2t
ns
CYC
2t
ns
CYC
2t
ns
CYC
0
ns
OE CEN CLK
DQ
X
L
L->H
Tri-State
X
L
L->H
Tri-State
X
L
L->H
Tri-State
X
L
L->H
Tri-State
L
L
L->H Data Out (Q)
L
L
L->H Data Out (Q)
H
L
L->H
Tri-State
H
L
L->H
Tri-State
X
L
L->H
Data In (D)
X
L
L->H
Data In (D)
X
L
L->H
Tri-State
X
L
L->H
Tri-State
X
H
L->H
–
X
X
X
Tri-State
BW
BW
A
B
X
X
H
H
H
H
H
H
L
L
= Tri-state when
[A:B]
Page 5 of 12
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