Cypress Semiconductor CY7C1298H Specification Sheet - Page 5

Browse online or download pdf Specification Sheet for Computer Hardware Cypress Semiconductor CY7C1298H. Cypress Semiconductor CY7C1298H 17 pages. Cypress 1-mbit (64k x 18) pipelined dcd sync sram specification sheet

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Functional Overview

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock.

The CY7C1298H

supports secondary cache in systems

utilizing either a linear or interleaved burst sequence. The

interleaved burst order supports Pentium and i486‰

processors. The linear burst sequence is suited for processors

that utilize a linear burst sequence. The burst order is user

selectable, and is determined by sampling the MODE input.

Accesses can be initiated with either the Processor Address

Strobe (ADSP) or the Controller Address Strobe (ADSC).

Address advancement through the burst sequence is

controlled by the ADV input. A two-bit on-chip wraparound

burst counter captures the first address in a burst sequence

and automatically increments the address for the rest of the

burst access.

Byte write operations are qualified with the Byte Write Enable

(BWE) and Byte Write Select (BW

Enable (GW) overrides all byte write inputs and writes data to

all four bytes. All writes are simplified with on-chip

synchronous self-timed write circuitry.

Synchronous Chip Selects CE

asynchronous Output Enable (OE) provide for easy bank

selection and output tri-state control. ADSP is ignored if CE

is HIGH.

Single Read Accesses

This access is initiated when the following conditions are

satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)

chip selects are all asserted active, and (3) the write signals

(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE

is HIGH. The address presented to the address inputs is

stored into the address advancement logic and the Address

sponding data is allowed to propagate to the input of the

Output Registers. At the rising edge of the next clock the data

is allowed to propagate through the output register and onto

the data bus within t

if OE is active LOW. The only exception

occurs when the SRAM is emerging from a deselected state

to a selected state, its outputs are always tri-stated during the

first cycle of the access. After the first cycle of the access, the

outputs are controlled by the OE signal. Consecutive single

read cycles are supported.

The CY7C1298H is a double-cycle deselect part. Once the

SRAM is deselected at clock rise by the chip select and either

ADSP or ADSC signals, its output will tri-state immediately

after the next clock rise.

Single Write Accesses Initiated by ADSP

This access is initiated when both of the following conditions

are satisfied at clock rise: (1) ADSP is asserted LOW, and

(2) chip select is asserted active. The address presented is

loaded

into

the

address

advancement logic while being delivered to the memory core.

The write signals (GW, BWE, and BW

ignored during this first cycle.

ADSP triggered write accesses require two clock cycles to

complete. If GW is asserted LOW on the second clock rise, the

data presented to the DQx inputs is written into the corre-

sponding address location in the memory core. If GW is HIGH,

then the write operation is controlled by BWE and BW

Document #: 38-05665 Rev. *B

) inputs. A Global Write

[A:B]

, CE

and an

and

the

address

) and ADV inputs are

[A:B]

signals. The CY7C1298H provides byte write capability that

is described in the Write Cycle Description table. Asserting the

Byte Write Enable input (BWE) with the selected Byte Write

input will selectively write to only the desired bytes. Bytes not

selected during a byte write operation will remain unaltered. A

synchronous self-timed write mechanism has been provided

to simplify the write operations.

Because the CY7C1298H is a common I/O device, the Output

Enable (OE) must be deasserted HIGH before presenting data

to the DQ inputs. Doing so will tri-state the output drivers. As

a safety precaution, DQ are automatically tri-stated whenever

a write cycle is detected, regardless of the state of OE.

Single Write Accesses Initiated by ADSC

ADSC write accesses are initiated when the following condi-

tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is

deasserted HIGH, (3) chip select is asserted active, and (4)

the appropriate combination of the write inputs (GW, BWE,

and BW

) are asserted active to conduct a write to the

[A:B]

desired byte(s). ADSC triggered write accesses require a

single clock cycle to complete. The address presented is

loaded

into

the

address

advancement logic while being delivered to the memory core.

The ADV input is ignored during this cycle. If a global write is

conducted, the data presented to the DQ

corresponding address location in the memory core. If a byte

write is conducted, only the selected bytes are written. Bytes

not selected during a byte write operation will remain

unaltered. A synchronous self-timed write mechanism has

been provided to simplify the write operations.

Because the CY7C1298H is a common I/O device, the Output

Enable (OE) must be deasserted HIGH before presenting data

to the DQ

inputs. Doing so will tri-state the output drivers. As

a safety precaution, DQ

whenever a write cycle is detected, regardless of the state of

OE.

Burst Sequences

The CY7C1298H provides a two-bit wraparound counter, fed

by A

, that implements either an interleaved or linear burst

[1:0]

sequence. The interleaved burst sequence is designed specif-

ically to support Intel Pentium applications. The linear burst

sequence is designed to support processors that follow a

linear burst sequence. The burst sequence is user selectable

through the MODE input. Both read and write burst operations

are supported

Asserting ADV LOW at clock rise will automatically increment

the burst counter to the next address in the burst sequence.

Both read and write burst operations are supported.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ

places the SRAM in a power conservation "sleep" mode. Two

clock cycles are required to enter into or exit from this "sleep"

mode. While in this mode, data integrity is guaranteed.

Accesses pending when entering the "sleep" mode are not

considered valid nor is the completion of the operation

guaranteed. The device must be deselected prior to entering

the "sleep" mode. CEs, ADSP, and ADSC must remain

inactive for the duration of t

ZZREC

LOW.

CY7C1298H

and

the

address

is written into the

are automatically tri-stated

after the ZZ input returns

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