Cypress Semiconductor CY7C1302DV25 Specification Sheet - Page 14
Browse online or download pdf Specification Sheet for Computer Hardware Cypress Semiconductor CY7C1302DV25. Cypress Semiconductor CY7C1302DV25 19 pages. Cypress 9-mbit burst of two pipelined srams with qdrtm architecture specification sheet
Print Page[20]
Thermal Resistance
Parameter
Θ
Thermal Resistance (Junction to Ambient)
JA
Θ
Thermal Resistance (Junction to Case)
JC
[20]
Capacitance
Parameter
C
IN
C
CLK
C
O
AC Test Loads and Waveforms
0.75V
V
REF
OUTPUT
Z
= 50Ω
0
Device
Under
Test
ZQ
RQ =
250Ω
(a)
Switching Characteristics
Cypress
Consortium
Parameter
Parameter
[22]
t
Power
Cycle Time
t
t
CYC
KHKH
t
t
KH
KHKL
t
t
KL
KLKH
t
t
KHKH
KHKH
t
t
KHCH
KHCH
Set-up Times
t
t
SA
SA
t
t
SC
SC
t
t
SD
SD
Hold Times
t
t
HA
HA
t
t
HC
HC
t
t
HD
HD
Notes:
20. Tested initially and after any design or process change that may affect these parameters.
21. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V,Vref = 0.75V, RQ = 250W, V
pulse levels of 0.25V to 1.25V, and output loading of the specified I
22. This part has a voltage regulator that steps down the voltage internally; t
or write operation can be initiated.
Document #: 38-05625 Rev. *A
Description
Description
Input Capacitance
Clock Input Capacitance
Output Capacitance
V
REF
OUTPUT
R
= 50Ω
L
Device
Under
V
= 0.75V
ZQ
REF
Test
Over the Operating Range
Description
V
(typical) to the First Access Read or Write
CC
K Clock and C Clock Cycle Time
Input Clock (K/K and C/C) HIGH
Input Clock (K/K and C/C) LOW
K/K Clock Rise to K/K Clock Rise and C/C to C/C Rise (rising edge
to rising edge)
K/K Clock Rise to C/C Clock Rise (rising edge to rising edge)
Address Set-up to Clock (K and K) Rise
Control Set-up to Clock (K and K) Rise (RPS, WPS, BWS
D
Set-up to Clock (K and K) Rise
[17:0]
Address Hold after Clock (K and K) Rise
Control Signals Hold after Clock (K and K) Rise
(RPS, WPS, BWS
, BWS
)
0
1
D
Hold after Clock (K and K) Rise
[17:0]
/I
OL
Test Conditions
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA/JESD51.
Test Conditions
T
= 25°C, f = 1 MHz,
A
V
DD
V
DDQ
V
= 0.75V
REF
0.75V
R = 50Ω
0.25V
5 pF
RQ =
250Ω
(b)
[21]
and load capacitance shown in (a) of AC test loads.
OH
is the time power needs to be supplied above V
Power
CY7C1302DV25
165 FBGA Package Unit
16.7
2.5
Max.
5
= 2.5V.
6
= 1.5V
7
[21]
ALL INPUT PULSES
1.25V
0.75V
Slew Rate = 2 V/ns
167 MHz
Min.
Max.
10
6.0
2.4
2.4
2.7
3.3
0.0
2.0
0.7
, BWS
)
0.7
0
1
0.7
0.7
0.7
0.7
= 1.5V, input
DDQ
minimum initially before a read
DD
Page 14 of 18
°C/W
°C/W
Unit
pF
pF
pF
Unit
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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