Cypress Semiconductor CY7C1306BV25 Specification Sheet - Page 17
Browse online or download pdf Specification Sheet for Computer Hardware Cypress Semiconductor CY7C1306BV25. Cypress Semiconductor CY7C1306BV25 20 pages. Cypress 18-mbit burst of 2 pipelined sram with qdr architecture specification sheet
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Switching Waveforms
READ
WRITE
1
2
K
t KH
t KL
K
RPS
tSC
WPS
A0
A1
A
t SA t HA
D
D10
D11
Q
t KHCH
t KHCH
C
t KH
C
Notes:
24. t
, t
, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.
CHZ
CLZ
25. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, i.e., A0+1.
26. Outputs are disabled (High-Z) one clock cycle after a NOP.
27. In this example, if address A2 = A1 then data Q2 0= D10 and Q21 = D11. Write data is forwarded immediately as read results.This note applies to the whole diagram.
Document #: 38-05627 Rev. *A
[25, 26, 27]
READ
WRITE
3
4
t CYC
tHC
A2
A3
t SA
t HA
D30
D31
D50
t HD
t SD
Q00
t CLZ
t CO
t CO
t KL
t KHKH
READ
WRITE
NOP
5
6
7
t KHKH
A5
A4
D51
D60
t SD
Q01
Q20
t DOH
t DOH
tCYC
CY7C1303BV25
CY7C1306BV25
WRITE
NOP
8
9
A6
D61
t HD
Q21
Q40
Q41
t CHZ
DON'T CARE
UNDEFINED
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