Cypress Semiconductor CY7C1329H Specification Sheet - Page 11

Browse online or download pdf Specification Sheet for Computer Hardware Cypress Semiconductor CY7C1329H. Cypress Semiconductor CY7C1329H 17 pages. 2-mbit (64k x 32) pipelined sync sram

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Switching Waveforms

[17]
Read Cycle Timing
t CYC
CLK
t
t
CL
CH
t
t
ADH
ADS
ADSP
ADSC
t AS
t AH
ADDRESS
A1
t WES
GW, BWE,
BW[A:D]
t CES
t CEH
CE
ADV
OE
Data Out (Q)
High-Z
Note:
17. On this diagram, when CE is LOW, CE
Document #: 38-05673 Rev. *B
t ADS
t ADH
A2
t WEH
t ADVS
t ADVH
t OEV
t CO
t OEHZ
t OELZ
t DOH
t CLZ
Q(A2)
Q(A1)
t CO
Single READ
DON'T CARE
is LOW, CE
is HIGH and CE
is LOW. When CE is HIGH, CE
1
2
3
ADV
suspends
burst.
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
BURST READ
UNDEFINED
is HIGH or CE
1
CY7C1329H
A3
Burst continued with
new base address
Deselect
cycle
t CHZ
Q(A2)
Q(A2 + 1)
Burst wraps around
to its initial state
is LOW or CE
is HIGH.
2
3
Page 11 of 16
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