Cypress Semiconductor CY7C1334H Specification Sheet

Browse online or download pdf Specification Sheet for Computer Hardware Cypress Semiconductor CY7C1334H. Cypress Semiconductor CY7C1334H 14 pages. 2-mbit (64k x 32) pipelined sram with nobl architecture

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Features
• Pin compatible and functionally equivalent to ZBT™
devices
• Internally self-timed output buffer control to eliminate
the need to use OE
• Byte Write capability
• 64K x 32 common I/O architecture
• 3.3V core power supply
• 3.3V/2.5V I/O operation
• Fast clock-to-output times
— 3.5 ns (for 166-MHz device)
— 4.0 ns (for 133-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed write
• Asynchronous output enable (OE)
• Offered in Lead-Free JEDEC-standard 100-pin TQFP
package
• Burst Capability—linear or interleaved burst order
• "ZZ" Sleep mode option
Logic Block Diagram
A0, A1, A
MODE
CLK
C
CEN
WRITE ADDRESS
REGISTER 1
ADV/LD
BW
A
BW
B
BW
C
BW
D
WE
OE
CE1
CE2
CE3
ZZ
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05678 Rev. *B
2-Mbit (64K x 32) Pipelined SRAM with
ADDRESS
REGISTER 0
A1
D1
Q1
A0
BURST
D0
Q0
LOGIC
ADV/LD
C
WRITE ADDRESS
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
READ LOGIC
SLEEP
CONTROL
•
198 Champion Court
NoBL™ Architecture
Functional Description
The
CY7C1334H
is
synchronous-pipelined Burst SRAM designed specifically to
support unlimited true back-to-back Read/Write operations
without the insertion of wait states. The CY7C1334H is
equipped with the advanced No Bus Latency™ (NoBL™) logic
required to enable consecutive Read/Write operations with
data being transferred on every clock cycle. This feature
dramatically improves the throughput of the SRAM, especially
in systems that require frequent Write/Read transitions.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal,
which, when deasserted, suspends operation and extends the
previous clock cycle. Maximum access delay from the clock
rise is 3.5 ns (166-MHz device)
Write operations are controlled by the four Byte Write Select
(BW
) and a Write Enable (WE) input. All writes are
[A:D]
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated
during the data portion of a write sequence.
A1'
A0'
S
E
N
S
E
MEMORY
WRITE
ARRAY
A
DRIVERS
M
P
S
INPUT
E
REGISTER 1
,
•
San Jose
CA 95134-1709
CY7C1334H
[1]
a
3.3V/2.5V,
64K
x
, CE
, CE
) and an
1
2
3
O
D
U
A
T
P
T
U
A
T
S
B
DQs
T
U
F
E
F
E
E
R
R
I
S
N
E
E
G
INPUT
E
REGISTER 0
•
408-943-2600
Revised February 6, 2006
32
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