Cypress Semiconductor CY7C1338G Specification Sheet - Page 12
Browse online or download pdf Specification Sheet for Computer Hardware Cypress Semiconductor CY7C1338G. Cypress Semiconductor CY7C1338G 18 pages. Cypress 4-mbit (128k x 32) flow-through sync sram specification sheet
Print PageTiming Diagrams
(continued)
[17, 18]
Write Cycle Timing
CLK
t ADS
ADSP
ADSC
t AS
ADDRESS
A1
BWE,
BW
[A:D]
GW
t CES
CE
ADV
OE
Data in (D)
High-Z
Data Out (Q)
BURST READ
Note:
18. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW
Document #: 38-05521 Rev. *D
t CYC
t
t
CL
CH
t ADH
t ADS
t ADH
t AH
A2
Byte write signals are ignored for first cycle when
ADSP initiates burst
t CEH
t
t
DS
DH
D(A2)
D(A1)
t
OEHZ
Single WRITE
ADSC extends burst
t
t
WES
WEH
ADV suspends burst
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
BURST WRITE
DON'T CARE
UNDEFINED
LOW.
[A:D]
CY7C1338G
t ADS
t ADH
A3
t WES
t WEH
t ADVS
t ADVH
D(A2 + 3)
D(A3)
D(A3 + 1)
Extended BURST WRITE
Page 12 of 17
D(A3 + 2)