Cypress Semiconductor CY7C1339G Specification Sheet

Browse online or download pdf Specification Sheet for Computer Hardware Cypress Semiconductor CY7C1339G. Cypress Semiconductor CY7C1339G 18 pages. Cypress 4-mbit (128k x 32) pipelined sync sram specification sheet

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Cypress Semiconductor CY7C1339G Specification Sheet
Features
• Registered inputs and outputs for pipelined operation
• 128K × 32 common I/O architecture
• 3.3V core power supply (V
• 2.5V/3.3V I/O power supply (V
• Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
• Provide high-performance 3-1-1-1 access rate
• User-selectable burst counter supporting Intel
®
Pentium
interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous output enable
• Available in lead-free 100-Pin TQFP package, lead-free
and non-lead-free 119-Ball BGA package
• "ZZ" Sleep Mode Option
Logic Block Diagram
A 0, A 1, A
M ODE
A DSC
A DSP
BW
BW
1
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05520 Rev. *F
4-Mbit (128K x 32) Pipelined Sync SRAM
)
DD
)
DDQ
®
A DDRESS
REGISTER
2
A DV
BURST
CLK
COUNTER
A ND
CLR
LOGIC
DQ
D
BYTE
D
W RITE REGISTER
DQ
C
BYTE
C
W RITE REGISTER
DQ
B
BYTE
BW
B
W RITE REGISTER
DQ
A
BYTE
BW
A
W RITE REGISTER
BW E
GW
ENA BLE
PIPELINED
CE
1
REGISTER
ENABLE
CE
2
CE
3
OE
SLEEP
ZZ
CONTROL
•
198 Champion Court
Functional Description
The CY7C1339G SRAM integrates 128K x 32 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
(CE
), depth-expansion Chip Enables (CE
1
Control inputs (ADSC, ADSP, and ADV), Write Enables
(BW
, and BWE), and Global Write ( GW ). Asynchronous
[A:D]
inputs include the Output Enable (OE) and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to four bytes wide as
controlled by the byte write control inputs. GW when active
LOW causes all bytes to be written.
The CY7C1339G operates from a +3.3V core power supply
while all outputs may operate with either a +2.5 or +3.3V
supply. All inputs and
JESD8-5-compatible.
A
[1:0]
Q1
Q0
DQ
D
BYTE
W RITE DRIVER
DQ
C
BYTE
W RITE DRIVER
M EM ORY
SENSE
A RRA Y
A M PS
DQ
B
BYTE
W RITE DRIVER
DQ
A
BYTE
W RITE DRIVER
,
•
San Jose
CA 95134-1709
CY7C1339G
[1]
and CE
), Burst
2
3
outputs
are
JEDEC-standard
OUTPUT
OUTPUT
D Q s
BUFFERS
REGISTERS
E
INPUT
REGISTERS
•
408-943-2600
Revised July 5, 2006
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