Cypress Semiconductor CY7C1364C Specification Sheet - Page 18

Browse online or download pdf Specification Sheet for Computer Hardware Cypress Semiconductor CY7C1364C. Cypress Semiconductor CY7C1364C 19 pages. 9-mbit (256k x 32) pipelined sync sram

Print Page

Document History Page

Document Title: CY7C1364C 9-Mbit (256K x 32) Pipelined Sync SRAM

Document Number: 38-05689

REV.

ECN NO.

286269

320834

377095

408725

429278

501828

Document #: 38-05689 Rev. *E

Orig. of

Issue Date

Change

See ECN

PCI

New data sheet

See ECN

PCI

Changed 225 MHz into 250 MHz

Changed Θ

respectively

Modified V

Added Industrial Operating Range

Changed Snooze to Sleep in the ZZ Mode Electrical Characteristics

Shaded 250 MHz speed bin in the AC/DC table and Selection Guide

Added AJXC package in the Ordering Information

Updated Ordering Information Table

See ECN

PCI

Changed I

Modified test condition in note# 9 from V

See ECN

RXU

Changed address of Cypress Semiconductor Corporation on Page# 1 from

"3901 North First Street" to "198 Champion Court"

Changed three-state to tri-state

Converted from Preliminary to Final

Modified "Input Load" to "Input Leakage Current except ZZ and MODE" in the

Electrical Characteristics Table

Replaced Package Name column with Package Diagram in the Ordering

Information table

Updated the ordering information

See ECN

NXR

Added 2.5 V I/O option

Included 2 Chip Enable Pinout

Updated Ordering Information Table

See ECN

VKN

Added the Maximum Rating for Supply Voltage on V

Updated the Ordering Information table.

Description of Change

and Θ

for TQFP from 25 and 9 °C/W to 29.41 and 6.13 °C/W

test conditions

OL,

from 30 to 40 mA

SB2

CY7C1364C

< V

to V

Relative to GND

DDQ

Page 18 of 18

[+] Feedback