Cypress Semiconductor CY7C150 Specification Sheet - Page 5
Browse online or download pdf Specification Sheet for Computer Hardware Cypress Semiconductor CY7C150. Cypress Semiconductor CY7C150 11 pages. 1kx4 static ram
Print PageSwitching Waveforms
Write Cycle No. 2 (CS Controlled)
ADDRESS
CE
WE
DATA IN
DATA I/O
[13]
Reset Cycle
ADDRESS
WE
CS
RESET
DATA I/O
Notes:
12. If CS goes HIGH with WE HIGH, the output remains in a high-impedance state.
13. Reset cycle is defined by the overlap of RS and CS for the minimum reset pulse width.
Document #: 38-05024 Rev. **
(continued)
[8,12]
t
SA
t
AW
DATA UNDEFINED
t
SAR
t
SWER
t
SCSR
t
PRS
t
HZRS
t
WC
t
SCS
t
PWE
t
SD
DATA
VALID
IN
t
HZWE
HIGH IMPEDANCE
t
RRC
t
HAR
t
HWER
t
HCSR
t
LZRS
HIGH
IMPEDANCE
CY7C150
t
HA
t
HD
C150-8
OUTPUT VALID ZERO
C150-9
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