Cypress Semiconductor Perform CY62138CV25 Specification Sheet
Browse online or download pdf Specification Sheet for Computer Hardware Cypress Semiconductor Perform CY62138CV25. Cypress Semiconductor Perform CY62138CV25 14 pages. 2-mbit (256k x 8) static ram mobl
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Features
• Very high speed: 45 ns
• Wide voltage range: 2.20V–3.60V
• Pin compatible with CY62138CV25/30/33
• Ultra low standby power
— Typical standby current: 1 µA
— Maximum standby current: 5 µA
• Ultra low active power
— Typical active current: 1.6 mA @ f = 1 MHz
• Easy memory expansion with CE
• Automatic power down when deselected
• CMOS for optimum speed and power
• Offered in Pb-free 36-ball VFBGA, 32-pin TSOP II, 32-pin
SOIC, 32-pin TSOP I and 32-pin STSOP packages
Logic Block Diagram
CE 1
CE 2
Note
1. For best practice recommendations, refer to the Cypress application note "System Design Guidelines" at
Cypress Semiconductor Corporation
Document #: 001-08029 Rev. *E
, CE
and OE features
1
2,
DATA IN DRIVERS
A 0
A 1
A 2
A 3
A 4
A 5
256K x 8
A 6
A 7
ARRAY
A 8
A 9
A 10
A 11
COLUMN DECODER
WE
OE
•
198 Champion Court
CY62138FV30 MoBL
2-Mbit (256K x 8) Static RAM
Functional Description
The CY62138FV30 is a high performance CMOS static RAM
organized as 256K words by 8 bits. This device features
advanced circuit design to provide ultra low active current.
This is ideal for providing More Battery Life™ (MoBL
portable applications such as cellular telephones. The device
also has an automatic power down feature that significantly
reduces power consumption. Place the device into standby
mode reducing power consumption when deselected (CE
HIGH or CE
LOW).
2
To write to the device, take Chip Enable (CE
HIGH) and Write Enable (WE) inputs LOW. Data on the eight
IO pins (IO
through IO
) is then written into the location
0
7
specified on the address pins (A
To read from the device, take Chip Enable (CE
HIGH) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins appear on
the IO pins.
The eight input and output pins (IO
in a high impedance state when the device is deselected (CE
HIGH or CE
LOW), the outputs are disabled (OE HIGH), or
2
during a write operation (CE
LOW).
POWER
DOWN
http://www.cypress.com.
,
•
San Jose
CA 95134-1709
[1]
®
) in
LOW and CE
1
through A
).
0
17
LOW and CE
1
through IO
) are placed
0
7
LOW and CE
HIGH and WE
1
2
IO 0
IO 1
IO 2
IO 3
IO 4
IO 5
IO 6
IO 7
•
408-943-2600
Revised March 26, 2007
®
1
2
2
1
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