Cypress Semiconductor Rambus XDR CY24271 Specification Sheet - Page 4

Browse online or download pdf Specification Sheet for Computer Hardware Cypress Semiconductor Rambus XDR CY24271. Cypress Semiconductor Rambus XDR CY24271 13 pages. Clock generator with zero sda hold time

Cypress Semiconductor Rambus XDR CY24271 Specification Sheet
Table 5. Modes of Operation for CY24272
EN
/BYPASS RegTest RegA RegB RegC RegD CLK0/CLK0B
L
X
X
H
X
1
H
L
0
H
H
0
H
H
0
H
H
0
H
H
0
H
H
0
H
H
0
H
H
0
H
H
0
H
H
0
H
H
0
H
H
0
H
H
0
H
H
0
H
H
0
H
H
0
[4]
H
H
0
Device ID and SMBus Device Address
The device ID (ID0 and ID1) is a part of the SMBus device 8-bit
address. The least significant bit of the address designates a
write or read operation.
Table 4
for four CY24272 devices on the same SMBus.
SMBus Protocol
The CY24272 is a slave receiver supporting operations in the
word and byte modes described in sections 5.5.4 and 5.5.5 of
the SMBus Specification 2.0.
DC specifications are modified to Rambus standard to support
1.8, 2.5, and 3.3 volt devices. Time out detection and packet
error protocol SMBus features are not supported.
Hold time for SDA is reduced relative to the CY24271, so that it
2
is compatible with I
C.
Notes
3. Bypass Mode: REFCLK bypasses the PLL to the output drivers.
4. Default mode of operation is at power up.
Document Number: 001-42414 Rev. **
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
[4]
[4]
[4]
[4]
1
1
1
1
on page 3 shows the addresses
CLK1/CLK1B CLK2/CLK2B CLK3/CLK3B
High Z
High Z
Reserved for Vendor Test
REFCLK/
REFCLK/
[3]
REFCLKB
REFCLKB
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
CLK/CLKB
High Z
CLK/CLKB
High Z
CLK/CLKB
High Z
CLK/CLKB
CLK/CLKB
High Z
CLK/CLKB
High Z
CLK/CLKB
High Z
CLK/CLKB
High Z
CLK/CLKB
CLK/CLKB
CLK/CLKB
CLK/CLKB
CLK/CLKB
CLK/CLKB
CLK/CLKB
CLK/CLKB
SMBus Data Byte Definitions
Three data bytes are defined for the CY24272. Byte 0 is for
programming the PLL multiplier registers and clock output
registers.
The definition of Byte 2 is shown in
on page
5. The upper five bits are the revision numbers of the
device and the lower three bits are the ID numbers assigned to
the vendor by Rambus.
CY24272
High Z
High Z
REFCLK/
REFCLK/
REFCLKB
REFCLKB
High Z
High Z
High Z
CLK/CLKB
CLK/CLKB
High Z
CLK/CLKB
CLK/CLKB
High Z
High Z
High Z
CLK/CLKB
CLK/CLKB
High Z
CLK/CLKB
CLK/CLKB
High Z
High Z
High Z
CLK/CLKB
CLK/CLKB
High Z
CLK/CLKB
CLK/CLKB
High Z
High Z
High Z
CLK/CLKB
CLK/CLKB
High Z
CLK/CLKB
CLK/CLKB
Table
6,
Table
7, and
Table 8
Page 4 of 13
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