Cypress Semiconductor Rambus XDR CY24272 Specification Sheet - Page 10
Browse online or download pdf Specification Sheet for Computer Hardware Cypress Semiconductor Rambus XDR CY24272. Cypress Semiconductor Rambus XDR CY24272 13 pages. Clock generator with zero sda hold time
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Test and Measurement Setup
Swing Current
Control
ISET
Example External Resistor Values
and Termination Voltages for a 50Ω Channel
Parameter
R
1
R
2
R
3
R
T1
R
T2
C
S
R
RC
V
TS
V
T
Signal Waveforms
A physical signal that appears at the pins of a device is deemed
valid or invalid depending on its voltage and timing relations with
other signals. Input and output voltage waveforms are defined as
shown in
Figure 4
on page 11. Both rise and fall times are defined
between the 20% and 80% points of the voltage swing, with the
swing defined as V
–V
.
H
L
Notes
19. Max and min output clock cycle times are based on nominal outputs frequency of 300 and 667 MHz, respectively. For spread spectrum modulated differential or
single-ended REFCLK, the output clock tracks the modulation of the input.
20. Output short term jitter spec is the absolute value of the worst case deviation.
is the timing difference between any two of the four differential clocks and is measured at common mode voltage. Δ t
21. t
SKEW
operating temperature and supply voltage change.
22. t
applies only when appropriate R
CR,CF
Document Number: 001-42414 Rev. **
Figure 3. Clock Outputs
CLK
Differential Driver
R
RC
CLKB
Value
Unit
Ω
33.0
Ω
18.0
Ω
17.0
Ω
60.4
Ω
301
2700
pF
Ω
432
2.5V
V
1.2V
V
and output resistor network resistor values are selected to match pull up and pull down currents.
RC
Measurement
V
Point
TS
R
Z
1
CH
R
R
C
2
3
S
Measurement
V
Point
TS
R
Z
1
CH
R
R
C
2
3
S
Figure 5
on page 11 shows the definition of the output crossing
point. The nominal crossing point between the complementary
outputs is defined as the 50% point of the DC voltage levels.
There are two crossing points defined: Vx+ at the rising edge of
CLK and Vx– at the falling edge of CLK. For some waveforms,
both Vx+ and Vx– are below Vx,nom (for example, if t
than t
).
CF
Jitter
This section defines the specifications that relate to timing uncer-
tainty (or jitter) of the input and output waveforms.
page 11 shows the definition of cycle-to-cycle jitter with respect
to the falling edge of the CLK signal. Cycle-to-cycle jitter is the
difference between cycle times of adjacent cycles. Equal require-
ments apply rising edges of the CLK signal.
shows the definition of cycle-to-cycle duty cycle error (t
Cycle-to-cycle duty cycle is defined as the difference between
t
(high times) of adjacent differential clock cycles. Equal
PW+
requirements apply to t
cycles.
CY24272
V
T
R
T1
R
T2
V
T
R
T1
R
T2
CR
Figure 6
Figure 7
on page 11
, low times of the differential click
PW-
is the change in t
SKEW
SKEW
Page 10 of 13
is larger
on
).
DC,ERR
when the
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