EG&G ORTEC 553 Operating And Service Manual - Page 12

Browse online or download pdf Operating And Service Manual for Measuring Instruments EG&G ORTEC 553. EG&G ORTEC 553 16 pages. Timing single-channel analyzer

Print Page

Integrated circuit ICS is the OF discriminator. The inputs

at its pins 3 and 4 are indicated in Fig. 4.1. During

operation, the ICS package is triggered at the beginning

of each input pulse, as soon as the S0% level at pin 4

exceeds the 2S% level at pin 3 by just a few millivolts.

Then, during decay of the input pulse, the level at pin 4

drops down through the level at pin 3 at S0% of the peak

amplitude, which is a dependable and precise time in a

shaped linear pulse, and ICS is reset. At reset, ICS(9)

goes high to drive pin 9 of ICS low and to switch IC6(1)

from low to high. R77 and C34 provide a slight delay

before IC6(1) reaches a high level and, during this short

interval, IC8(10) goes high. The level at IC8(10) Is one of

the three inputs to SCA Gate IC7(12).

The CF discriminator is triggered and then reset during

each input pulse, including noise pulses. The only input

pulses that will use the time-significant CF reset are

those that also trigger the LL discriminator.

5.9.

SCA GATE

Integrated circuit IC7(12) is the SCA Gate. When all

three of its inputs are high, the output switches low and

this starts generation of an output through the Pos Out

and the Neg Out connectors.

The signal at 107(13) is high unless the upper level

discriminator has been triggered and switch 81 is set at

either Nor or Win (the differential mode of operation). A

response by the UL discriminator, with differential oper

ation, will inhibit a response in IC7(12).

The signal at IC7(2) is high from the time the LL discrim

inator is triggered until an internal reset is generated by

IC7(6), and this will not occur before the reset of the CF

discriminator. Thus a response by the LL discriminator is

a prerequisite to enable gate IC7(12).

The signal at IC7(1) is furnished from IC8(10) when the

CF discriminator is reset (see Section 5.8). Thus, for the

short duration of the signal high at IC7(1), and if the

single-channel criteria have been met by signals at

IC7(2) and IC7(13), then IC7(12) will go low.

5.10.

RESET CIRCUIT

An internal reset circuit is furnished from IC7(6), going

low when all three inputs are high. When IC7(6) goes

low, it resets the latch for the LL discriminator through

IC6(13): it resets the latch for the UL discriminator (if it

has been triggered) through IC6(10); and it turns on Q11

to quickly discharge the storage capacitor CIO in the

peak detect circuit.

At the start of an input signal, at the CF trigger response,

the input of IC7(6) at pin 3 goes low and remains low

until just after the CF discriminator is reset [the signal

from IC6(1), R77, and C34].

The signal at pin 4 goes high at the LL discriminator

trigger time and is latched high through IC4(11) until

internal reset has occurred.

The third input to IC7(6) is furnished from the comple

mentary output of IC4(9) and this goes high when IC4 is

reset. The IC4 reset occurs when the input signal ampli

tude decays back through the adjusted LL threshold.

From a timing point of view, the LL trigger and reset must

have both occurred and the CF discriminator must have

been reset before all three inputs to IC7(6) can be high

simultaneously. Either the CF or the LL reset can occur

before the other, but the reset trigger depends on both

events having occurred. The duration of the low signal

from IC7(6) is the propagation time for the reset of latch

IC6(13) and IC4(11).

Since the reset circuit is dependent upon the lower level

discriminator, and since in the Normal and Integral

modes it is possible to adjust the upper level threshold

for a response at less than the lower level threshold, this

combination could result in a single response through

the UL Out without its latch being reset until the lower

level threshold is also exceeded by an input. This condi

tion will not exist in the Window mode, since it is not

possible to set the UL below the LL level.

5.11.

DELAY CIRCUIT

When IC7(12) goes low (Section 5.9), IC8(13) goes high

and triggers the delay circuit. The delay circuit includes

Q15, Q16, Q19, Q20, and Q21 and their associated

circuitry. When the trigger is furnished to Q15, Q16 is cut

off and held in the off state by the signal from Q21 and

C45. Q16 then returns to its normally conducting condi

tion when C45 is recharged by current through Q19.

When Q16 is turned on again, the negative output transi

tion triggers the SCA outputs.

Potentiometer R115, the Delay control on the front panel,

combines with the Q19E level to determine the current

rate that will recharge 045 and thus determine the

recovery time for the delay circuit.

Pin 9 of 109 is held high and at the start of the delay

interval, pin 10 of 109 goes high and this propagates

through 109(11) and 109(6) to furnish a low to pin 3 of

1010(1), arming this gate. At the negative transition from

Q160, 109(8) switches high so 109(3) goes low and

triggers the current switch Q13 and Q14 for the Neg Out

signal; the negative transition also triggers 1010(1) to

furnish a negative pulse through 1010(4) and start the

generation of the Pos Out signal. Both of these triggers

are terminated by the fast differentiation of R89 and 038.

The base level for 016 is very sensitive, so a temperature

compensating network is connected between this point

and ground.

5.12.

DC POWER

Input power from the bin and power supply is accepted

through the module connector on the rear panel. The 553

operates on 82 mA through the -1-24 V circuit, 160 mA

through the -1-12 V source, 50 mA from -24 V, and 120 mA

from -12 V.

Internally, the +12 V source is furnished to a circuit that

uses Q32 and Q33 to generate a regulated +5 V level. The

+5 V level is used in the integrated circuit packages that

are in the 553 circuits.