ComBlock COM-1826 Handmatig - Pagina 10

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with decoded data.

Example : 0x AC 10 01 80 designates

address 172.16.1.128

The new address becomes effective

immediately (no need to reset the

ComBlock).

REG45 (MSB) – REG48(LSB)

Destination ports

I-channel data is routed to this user-defined

port number:

REG49(LSB) – REG50(MSB)

Q-channel data is routed to the incremented

port number.

Subnet mask

REG51 (MSB) – REG54(LSB)

Gateway IP address REG55 (MSB) – REG58(LSB)

(Re-)Writing to the last control register REG81 is

recommended after a configuration change to enact the

change.

Status Registers

Parameters

Monitoring

Hardware self-

At power-up, the hardware platform

check

performs a quick self check. The result is

stored in status registers SREG0-9

Properly operating hardware will result in

the following sequence being displayed:

SREG0-SREG9 = 01 F1 1D xx 1F 93 10

22 22 03

TCXO reference

1 = detected

clock presence

0 = missing

SREG9(0)

125 MHz internal

Indirectly confirms the presence of the

clock PLL lock

frequency reference (TCXO for firmware

option –A, external 10 MHz for firmware

option –B)

1 = locked

0 = unlocked

SREG9(1)

Input sampling rate

The sampling rate, as read from the SDDS

input stream.

Format:

sampling_rate/fclk *2^32

SREG10 = bit 7-0 (LSB)

SREG11 = bit 15 – 8

SREG12 = bit 23 – 16

SREG13(3:0) = bit 27 – 24 (MSB)

Time tag

Last valid timetag read from the SDDS

input header. Expressed in 250ps units.

SREG14 (LSB) – SREG21(MSB)

Input frame counter

Cumulative SDDS frame counter. Each

frame contains 1024 bytes = 256 complex

samples.

SREG22 (LSB) – SREG25(MSB)

Missing input frame

Cumulative number of missing SDDS

counter

frames. Should be zero.

SREG26 (LSB) – SREG27(MSB)

LAN1 MAC bad

SREG28 (LSB) – SREG29(MSB)

CRC counter

MAC address

Unique 48-bit hardware address (802.3). In

the form SREG30:SREG31:SREG32:

...:SREG35

Demodulator

SREG36(0)

carrier lock status

0 = unlocked or no input

1 = locked

Code lock status SREG36(1)

0 = unlocked or no input

1 = locked (1 s hysteresis)

Viterbi decoder1

SREG36(2)

synchronized

0 = not synchronized or no input

1 = synchronized

Viterbi decoder2 SREG36(3)