Fujitsu LQFP-100P Bedieningshandleiding - Pagina 12
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■ MCU board I/F connector(CN1/CN2/CN3)
CN1 and CN2 are MCU board I/F connectors. CN3 is the incorrect insertion prevention socket of a
MCU board. The pin assignment of the MCU board I/F connector CN1 is shown in Table 5, and the
pin assignment of the MCU board I/F connector CN2 is shown in Table 6.
Connector
Evaluation
Pin
MCU Pin
Numbers
Numbers
1
A9
2
B9
3
C9
4
D9
5
A8
6
B8
7
C8
8
D8
9
A7
10
B7
11
C7
12
D7
13
A6
14
B6
15
C6
16
D6
17
A5
18
B5
19
C5
20
D5
21
A4
22
A3
⎯
23
⎯
24
25
A2
26
A1
27
B4
28
B3
29
B2
30
B1
31
C4
32
C3
33
C2
34
C1
35
D4
36
D3
37
D2
38
D1
39
E4
40
E3
Table 5 Pin assignment of the MCU board I/F connector CN1
Connector
Signal
Pin
name
Numbers
PC4
41
PC1
42
PC2
43
PC3
44
PC0
45
PB4
46
PB5
47
PB6
48
PB7
49
PB2
50
PB0
51
PB1
52
PB3
53
PA2
54
P95
55
PA0
56
PA3
57
P94
58
P90
59
P91
60
PA1
61
P93
62
GND
63
GND
64
CSVENX
65
Vss
66
P92
67
TCLK
68
LVCC
69
LVDIN
70
Cpin
71
Vcc51
72
LVDENX2
73
LVR4
74
TESTO
75
LVDOUT
76
LVR2
77
BGOENX
78
LVR1
79
LVR0
80
Evaluation
Signal
MCU Pin
name
Numbers
E2
LVR3
E1
LVSS
F4
LVDREXT
F3
LVDBGR
F2
LVDENX
F1
P22A
⎯
GND
⎯
GND
G4
P20A
G3
NC1
G2
P21A
G1
P23A
H4
P24A
H3
P25A
H2
P26A
H1
P27A
J4
P24B
J3
P50
J2
P23B
J1
P51
K1
P52
K2
P55
K3
P54
K4
P53
L1
P70
L2
P74
L3
P73
L4
P72
M1
P71
M2
P76
M3
P80
M4
P77
⎯
GND
⎯
GND
N1
P75
N2
P82
N3
PG0
N4
P84
P1
P81
P2
ROMS0
Connector
Evaluation
Pin
MCU Pin
Numbers
Numbers
81
P3
82
P4
83
R1
84
R2
85
R3
86
R4
87
T1
88
T2
89
T3
90
T4
91
U1
92
U2
93
U3
94
U4
95
V1
96
V2
⎯
97
⎯
98
99
V3
100
V4
101
R5
102
T5
103
U5
104
V5
105
R6
106
T6
107
U6
108
V6
109
R7
110
T7
111
U7
112
V7
113
R8
114
T8
115
U8
116
V8
117
R9
118
T9
119
U9
120
V9
Signal
name
BSOUT
BDBMX
P83
BRSTX
X0A
RSTX
ROMS1
BSIN
Vss
X0
BEXCK
X1
MOD
PF2
X1A
Vcc53
GND
GND
PINT0
PSEL_EXT
PF1
PF0
NC2
PENABLE
APBENX
PINT1
PCLK
PADDR0
PACTIVE
PLOCK
PWRITE
PADDR1
PADDR2
PADDR3
PADDR4
PADDR5
PADDR7
PRDATA0
PADDR6
PRDATA1
9