Fujitsu MB91460 SERIES Toepassingsnotitie - Pagina 11
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2.5 Registers
2.5.1 Processor Status (PS)
The Processor Status contains three sub sections.
31
...
21
---
For Interrupts the Interrupt Level Mask (ILM) and the I-Bit of the Condition Code Register
(CCR) are important.
2.5.1.1 Interrupt Level Mask (ILM)
After reset the ILM is set to "01111". It should be noted that when the original value of ILM is
between 16 to 31 then the ILM can be only set with the values between 16 to 31 (both
inclusive). In such case if the value is between 0 to 15 is attempted to be written, then the
ILM would be set to the specified value + 16. Where as when the original value of ILM is
between 0 to 15, then any value between 0 to 31 can be set.
Value of ILM
0 to 14
16 to 30
31
The Level can be set in C with the language extension directive __set_il(n), where n is
the level. The machine instruction for this is MOV ILM,#n.
2
Peripheral Interrupts disabled if the ICR is set to this value.
© Fujitsu Microelectronics Europe GmbH
INTERRUPTS
Chapter 2 Interrupt Types
20
...
16
17
ILM
Table 2-3: Processor Status
Remarks
ILM is set to this value in case of exceptions
and traps.
In case of NMI, ILM is set to this value. All
15
the peripheral interrupt are disabled
Peripheral interrupts enabled those have
their ICR value less then ILM.
2
All interrupts are enabled.
Table 2-4: Interrupt Level Mask
...
11
10
...
---
SCR
- 11 -
8
7
...
0
CCR
MCU-AN-300055-E-V10