DG NVMe-IP Demo instructies - Pagina 9
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Pagina afdrukkendg_nvmeip_instruction_en.doc
7) Power on FPGA development board and AB16-PCIeXOVR board, as shown in Figure
2-10 and Figure 2-11.
8) Open Serial console such as TeraTerm, HyperTerminal. Set Buad rate=115,200 Data=8 bit
Non-Parity Stop=1.
30-Nov-17
Figure 2-10 Power switch on AB16 board
Figure 2-11 Power switch on FPGA board
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