Chrontel CH7515A Handleiding voor lay-outontwerp - Pagina 4

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CHRONTEL
U1
RB
XO
REFCK
CH7515A
NOTE: CH7515/CH7516 supports three
kinds of clock input ways
Option1: use 27MHz crystal with 22pf
capacitors
Option 2: inject clock 14.318MHz(3.3V) in
REFCK pin(Pin 10)
Option 3: inject clock 27MHz (3.3V) in
REFCK pin(Pin 10)
2.4
Serial Port Control Pins
• SPC0 and SPD0
SPD0 and SPC0 function as a serial interface where SPD0 is bi-directional data and SPC0 is an input only serial clock.
In the reference design, SPD0 and SPC0 pins are pulled up to VCC3_3 with 6.8kohm resistors. Through these two
pins, the internal register values of the chip can be read and can update the external Boot ROM. These pins should be
connecting to SPC1 and SPD1 with Jumpers as shown in Figure 4.
• SPC1 and SPD1
SPD1 and SPC1 function as a serial interface where SPD1 is bi-directional data and SPC1 is an input only serial clock.
In the reference design, SPD1 and SPC1 pins are pulled up to VCC3_3 with 6.8kohm resistors as shown in Figure 4.
SPD1 and SPC1 are used to interface with CH9904 (the serial BOOT ROM). From the BOOT ROM, the EDID and
Programmable Registers can be setting in BOOT ROM. When powering up, CH7515A will auto-load the values from
the BOOT ROM.
4
VCC18
R1
10K
1
6
7
XI
10
Figure 3: General Control Pins
VCC33
R2
10K
PMBS3904
3
1
Q2
3
R3
C1
Q1
1
2
1k
PMBS3904
2
0.1uF
Note:
The resetb is 1.8V level. It need 10Kohm
resister to 1.8V and
GND. So if the system reset signal is
3.3V,the level shift circuit is necessary.
1
REFCK
C2
18pF
2
206-1000-021
AN-B021
RB_PCH
0.1uf capacitor to
X1
4
3
GND
P2
1
2
P1
GND
644-1232-2-ND (27 MHz)
1
C3
18pF
2
Rev 1.0
2020-07-15