Chrontel CH7515A Handleiding voor lay-outontwerp - Pagina 8

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CHRONTEL

• PSEL [0:2]

These pins can be used as panel select signals. They can be pulled high or low forming into 8 different combinations.

Every combination can match with one panel type. The connection is shown Figure 9.

Method 1 (default)

PSEL [2:0] can be connected to high/low level by pull-up/pull-down resistors in CH7515A PCB board; CH7515A can

get correct LVDS Panel selection value upon power ON.

Method 2

PSEL [2:0] can be controlled by other chip's GPIO pins in CH7515A application system.

If the chip controlling CH7515A PSEL [2:0] cannot set expected value before CH7515A finishes loading. Its

firmware (typically 150ms after CH7515A power ON), then the controlling chip must reset CH7515A to restart

CH7515A Loading BOOT ROM file. It is recommended to reset CH7515A by the controlling chip each time LVDS

Panel selection value is changed.

The following figure shows the typical cases to control CH7515A PSEL [2:0] by other chip.

Case1 is the right loading case. The PSEL pins can keep stable values in 150ms after the reset signal is given to

CH7515A RB pin

Case2 is the wrong loading case. The PSEL pins cannot keep stable values in 150ms after the reset signal is given to

CH7515A RB pin. So the RB signal must be given again. The RB pulse width is recommended be larger than 10ms.

Figure 8: BLDN, BLUP, PWRDN and GPIO [0] Connections

+3.3V

PSEL[2]

PSEL[1]

PSEL[0]

CH7515A

Figure 9: PSEL [0:2] connections

10k

PSEL[1]

PSEL[0]

10k

206-1000-021

AN-B021

Rev 1.0

2020-07-15