EPC EPC9041 Snelstarthandleiding - Pagina 2

Blader online of download pdf Snelstarthandleiding voor {categorie_naam} EPC EPC9041. EPC EPC9041 5 pagina's. Monolithic half-bridge with gate drive development board
Ook voor EPC EPC9041: Snelstarthandleiding (5 pagina's)

Pagina afdrukken
QUICK START GUIDE
DESCRIPTION
These development boards are in a monolithic half-bridge topology with
on-board gate drives, featuring the EPC2105 eGaNIC (Enhancement-mode
Gallium Nitride Integrated Circuit). The purpose of these development
boards is to simplify the evaluation process of these monolithically
integrated eGaN FETs by including all the critical components on a single
board that can be easily connected into any existing converter.
The development board is 2" x 2" and contains one eGaNIC in half-bridge
configuration using the Texas Instruments LM5113 gate driver, supply and
bypass capacitors. The board contains all critical components and layout
for optimal switching performance and has additional area to add buck
output filter components on board. There are also various probe points
to facilitate simple waveform measurement and efficiency calculation.
A complete block diagram of the circuit is given in Figure 1.
For more information on the EPC2105 eGaNIC, please refer to the
datasheet available from EPC at www.epc-co.com. The datasheet should
be read in conjunction with this quick start guide.

SETUP AND OPERATION

The development boards are easy to set up to evaluate the performance
of the eGaNIC. The board allows the on-board placement of buck output
filter components. Refer to Figure 2 for proper connect and measurement
setup and follow the procedure below:
1. With power off, connect the input power supply bus to +V
ground / return to –V
(J7, J8).
IN
2. With power off, connect the switch node of the half bridge OUT (J3, J4)
to your circuit as required.
3. With power off, connect the gate drive input to +V
ground return to –V
(J1, Pin-2).
DD
4. With power off, connect the input PWM control signal to PWM
(J2, Pin-1) and ground return to any of the remaining J2 pins.
5. Turn on the gate drive supply – make sure the supply is between
7 V and 12 V range.
6. Turn on the bus voltage to the required value (do not exceed the
absolute maximum voltages).
7. Turn on the controller / PWM input source and probe switching node
to see switching operation.
8. Once operational, adjust the bus voltage and load PWM control within
the operating range and observe the output switching behavior,
efficiency and other parameters.
9. For shutdown, please follow steps in reverse.
NOTE. When measuring the high frequency content switch node (OUT), care must
be taken to avoid long ground leads. Measure the switch node (OUT) by placing
the oscilloscope probe tip through the large via on the switch node (designed for
this purpose) and grounding the probe directly across the GND terminals provided.
See Figure 3 for proper scope probe technique.
2 |
Table 1: Performance Summary (T
Symbol
V
DD
V
IN
V
OUT
I
OUT
V
PWM
*Maximum input voltage depends on inductive loading.
** Maximum current depends on die temperature – actual maximum current with be subject to switching frequency, bus
voltage and thermal cooling. Symmetrical eGaN intended for 50% duty cycle or low step-down ratio applications.
# Limited by time needed to 'refresh' high side bootstrap supply voltage.
V
DD
PWM
Input
(J5, J6) and
IN
(J1, Pin-1) and
DD
7 V – 12 V
_
V
Supply
DD
+
Gate Drive Supply
(Note Polarity)
+
V
V
IN
_
(For E ciency
Measurement)
PWM Input
| EPC – EFFICIENT POWER CONVERSION CORPORATION |
Demonstration System EPC9041
= 25°C) EPC9041
A
Parameter
Conditions
Gate Drive Input Supply Range
Bus Input Voltage Range
Switch Node Output Voltage
Switch Node Output Current
Input 'High'
PWM Logic Input Voltage Threshold
Input 'Low'
Minimum 'High' State Input Pulse
V
PWM
Width
time < 10ns
Minimum 'Low' State Input Pulse
V
PWM
Width
time < 10ns
Gate Drive Supply
Gate Drive
Regulator
Logic and
LM5113
Dead-time
Gate
Adjust
Driver
Figure 1: Block Diagram of Development Board
VERSION
EPC9041 DEVELOPMENTBOARD
P
GND
*
Figure 2: Proper Connection and Measurement Setup
WWW.EPC-CO.COM
Min Max Units
7
12
V
50*
V
50*
V
20**
A
3.5
6
V
0
1.5
V
rise and fall
50
ns
rise and fall
100#
ns
Monolithic
Half Bridge
V
IN
VSW
OUT
Pads for Buck Output Filter
See table for max
A
Pads for Buck
I
Output Filter
IN
+
V
Supply
V
IN
SW
_
50 V
V
OUT
+
V
V
OUT
_
(For E ciency
Measurement)
| COPYRIGHT 2017