Axxon LF755KB Installatiehandleiding - Pagina 17

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Installation Guide for Axxon LF755KB PCI Express (PCIe) 4 Port RS422 SMPTE I/O Card (Low/Standard Height Mounting)

6.0 Technical Details of Hardware and Software Design

This part of the documentation will discuss the low level hardware and software design for developers interested in

creating their own software interface to configure this adapter card.

Each port is configured through a dedicated MIO pin.

MIOx pin = High = Port is in MASTER (DTE) mode.

MIOx pin = Low = Port is in SLAVE

There are 4 of Single PCI UARTs present in this design.

Each PCI UART is indexed using the following IDs:

Vendor ID: 1415h

Device ID: 950Bh

Each PCI UART provides 2 of MIO pins. Only the first 2 PCI UARTs are used for the required 4 MIO pins to

configure the port modes.

Therefore,

UART_U2_MIO_0 = controls the mode for Port # 1 ; this is the first PCI UART in our design

UART_U2_MIO_1 = controls the mode for Port # 2

UART_U3_MIO_0 = controls the mode for Port # 3 ; this is the second PCI UART in our design

UART_U3_MIO_1 = controls the mode for Port # 4

Each mode configuration has a volatile (immediate configuration) and non-volatile (stored in EEPROM) setting.

An immediate configuration change may be made by manipulating the MIO pins for the respective port. The

following examples and procedure should clarify the steps required for a mode switch.

Configure Port # 1 and Port # 2 modes

Port # 1 is controlled by UART_U2_MIO_0 and Port # 2 through UART_U2_MIO_1 so search out the first UART

on the circuit board using the IDs noted above. In reviewing the documentation for the Oxford OXCB950 UART,

note that PCI BAR2 will point to the Local Configuration registers in I/O space.

Assume for this example that BAR2 = B400h

The MIO registers (MIC) are located at an offset of +0x04 within the Local Configuration registers.

Therefore the MIO pin register access will start @ B400h + 04h = B404h for this example.

Each MIO pin is defined using 2 bits with the following format:

00 = MIO pin is a non-inverting input pin ;

01 = MIO pin is an inverting input pin

10 = MIO pin is an output pin driving '0'

11 = MIO pin is an output pin driving '1

Axxon Computer Corporation

V1.0

(DCE) mode.

not applicable in this h/w design and an illegal state to use

;

not applicable in this h/w design and an illegal state to use

; will configure the Port to SLAVE (DCE) mode

; will configure the Port to MASTER (DTE) mode