Digilent Atlys Referentiehandleiding - Pagina 13
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AUD-RESET
E12
The EDK reference design (available on the Digilent website) sends a square wave signal to the left,
right, and then both audio channels on the LINE OUT jack, and loops back the LINE IN input to the
headphone output, and swaps the left and right channels in the process.
The ISE reference design simply un-mutes the codec channels and loops back LINE IN audio data to
the LINE OUT jack.
Oscillators/Clocks
The Atlys board includes a single 100MHz CMOS oscillator connected to pin L15 (L15 is a GCLK
input in bank 1). The input clock can drive any or all of the four clock management tiles in the Spartan-
6. Each tile includes two Digital Clock Managers (DCMs) and four Phase-Locked Loops (PLLs).
DCMs provide the four phases of the input frequency (0º, 90º, 180º, and 270º), a divided clock that
can be the input clock divided by any integer from 2 to 16 or 1.5, 2.5, 3.5... 7.5, and two antiphase
clock outputs that can be multiplied by any integer from 2 to 32 and simultaneously divided by any
integer from 1 to 32.
PLLs use VCOs that can be programmed to generate frequencies in the 400MHz to 1080MHz range
by setting three sets of programmable dividers during FPAG configuration. VCO outputs have eight
equally-spaced outputs (0º, 45º, 90º, 135º, 180º, 225º, 270º, and 315º) that can be divided by any
integer between 1 and 128.
USB-UART Bridge (Serial Port)
The Atlys includes an EXAR USB-UART bridge to allow PC applications to communicate with the
board using a COM port. Free drivers allow COM-based (i.e., serial port) traffic on the PC to be
seamlessly transferred to the Atlys
board using the USB port at J17
marked UART. The EXAR part
delivers the data to the Spartan-6
using a two-wire serial port with
software flow control (XON/XOFF).
Free Windows and Linux drivers can
be downloaded from www.exar.com. Typing the EXAR part number "XR21V1410" into the search box
will provide a link to the XR21V1410's land page, where links for current drivers can be found. After
the drivers are installed, I/O commands from the PC directed to the COM port will produce serial data
traffic on the A16 and B16 FPGA pins.
Doc: 502-178
down state on the codec AC Link interface.
Cold Reset. This active low signal causes a hardware reset which
returns the control registers and all internal circuits to their default
conditions. RESET must be used to initialize the LM4550 after Power
On when the supplies have stabilized. RESET also clears the codec
from both ATE and Vendor test modes. In addition, while active, it
switches the PC_BEEP mono input directly to both channels of the
LINE_OUT stereo output.
J17
"UART"
2
Micro-USB
XR21V1410
200
A16
TXD
RXD
B16
Spartan-6
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