Digilent Cerebot II Referentiehandleiding - Pagina 8

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Cerebot II Reference Manual
Pin
Description
JD
SPI interface
The SPI interface on JD is used for synchronous serial
communication of host processor and peripherals or for a
connection of two processors. Master or slave modes are
selected as part of the software.
Serial port communications and interrupts
Asynchronous serial port, UART1, as well as the Atmel TWI
interface can be accessed on JD. These pins can also be
used as external interrupt sources.
JE
H-bridge connection with input capture
This port can be used to provide two pulse width modulated
outputs to run two motors, or it can be used to run a single
motor with input sensing for a shaft encoder or other sensor.
The PmodHB3 or PmodHB5 can be used for this application.
JF
H-bridge connection, interrupts, and on-board LEDs
Use this port to run two motors, like JE, or a motor with input
sensing for a shaft encoder or other sensor. All of the pins on
this header give access to interrupt inputs, providing flexibility
for application development. JF can be used as a motor
controller or interrupt source. The onboard LEDs share pins
with this header and can display information.
JG
H-bridge connection
This port can be used to provide two pulse width modulated
outputs to run two motors, or it can be used to run a single
motor with input sensing for a shaft encoder or other sensor.
The PmodHB3 or PmodHB5 can be used for this application.
JH
Analog input
Inputs to the analog to digital converter of the ATmega64L.
ADC0 and ADC1 are connected to the Cerebot II's voltage
monitoring circuits. ADC0 is the input for monitoring VU board
power and ADC1 is connected to VS for monitoring the
independent servo power.
The default fuse setting for the Cerebot II is to disable the
JTAG input and provide analog inputs. The ATmega64L fuse
settings have to be changed to enable the JTAG interface to
use JH as a JTAG device input (e.g., to use the Atmel
JTAGICE mkII).
The pins on JH are shared with the servo connectors S1-S8.
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Cerebot II Pmod Header Pins to
ATmega64L Ports / Bit
Pin
Function
1
SS
2
MOSI
3
MISO
4
SCK
5
GND
6
VCC
7
SCL/ INT0
8
SDA/ INT1
9
RXD1/ INT2
10
TXD1/ INT3
11
GND
12
VCC
1
T1
2
OC1A
3
ICP1
4
OC1B
5
GND
6
VCC
1
T3/ INT6
2
OC3B/ INT4
3
ICP3/ INT7
4
OC3C/ INT5
5
GND
6
VCC
1
T2
2
OC0
3
XCK1
4
OC2/ OC1C
5
GND
6
VCC
1
ADC0
2
ADC1
3
ADC2
4
ADC3
5
GND
6
VCC
7
ADC5/ TMS
8
ADC7/ TDI
9
ADC6/ TDO
10
ADC4/ TCK
11
GND
12
VCC
Digilent, Inc.
Port / Bit
PB 0
PB 2
PB 3
PB 1
PD 0
PD 1
PD 2
PD 3
PD 6
PB 5
PD 4
PB 6
PE 6
PE 4
PE 7
PE 5
PD 7
PB 4
PD 5
PB 7
PF 0
PF 1
PF 2
PF 3
PF 5
PF 7
PF 6
PF 4
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