Motorola GM140 Service-informatie - Pagina 18

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2-8

THEORY OF OPERATION

The VCOBIC together with Fractional-N synthesizer (U4201) generates the required frequencies in

both transmit and receive modes. The TRB line (U4301 pin 19) determines which tank circuits and

internal buffers are to be enabled. A high level on TRB enables TX tank and TX output (pin 10), and

a low enables RX tank and RX output (pin 8). A sample of the signal from the enabled output is

routed from U4301 pin 12 (PRESC_OUT), via a low pass ﬁlter, to pin 32 of U4201 (PREIN).

A steering line voltage (VCTRL) between 3.0V and 10.0V at varactor diode CR4311 will tune the full

TX frequency range (TXINJ) from 403 MHz to 470 MHz, and at varactor diodes CR4301, CR4302

and CR4303 will tune the full RX frequency range (RXINJ) from 358 MHz to 425 MHz. The tank

circuits uses the Hartley conﬁguration for wider bandwidth. For the RX tank circuit, an external

transistor Q4301 is used in conjunction with the internal transistor for better side-band noise.

The external RX buffers (Q4332) are enabled by a high at U4201 pin 3 (AUX4) via transistor switch

Q4333. In TX mode the modulation signal (VCOMOD) from the LVFRAC-N synthesizer IC (U4201

pin41) is applied modulation circuitry CR4321, R4321, R4322 and C4324, which modulates the TX

VCO frequency via coupling capacitor C4321. Varactor CR4321 is biased for linearity from VSF.

4.4

Synthesizer Operation

The complete synthesizer subsystem comprises mainly of low voltage FRAC-N (LVFRACN) IC,

Reference Oscillator (crystal oscillator with temperature compensation), charge pump circuitry, loop

ﬁlter circuitry and DC supply. The output signal PRESC_OUT of the VCOBIC (U4301 pin12) is fed to

pin 32 of U4201 (PREIN) via a low pass ﬁlter (C4229, L4225) which attenuates harmonics and

provides the correct level to close the synthesizer loop.

The pre-scaler in the synthesizer (U4201) is basically a dual modulus pre-scaler with selectable

divider ratios. This divider ratio of the pre-scaler is controlled by the loop divider, which in turn

receives its inputs via the SRL. The output of the pre-scaler is applied to the loop divider. The output

of the loop divider is connected to the phase detector, which compares the loop divider´s output

signal with the reference signal.The reference signal is generated by dividing down the signal of the

reference oscillator (Y4261 or Y4262).

The output signal of the phase detector is a pulsed DC signal which is routed to the charge pump.

The charge pump outputs a current at pin 43 of U4201 (IOUT). The loop ﬁlter (which consists of

R4221-R4223, C4221-C4225,L4221) transforms this current into a voltage that is applied to the

varactor diodes CR4311 for transmit, CR4301, CR4302 & CR4303 for receive and alters the output

frequency of the VCO .The current can be set to a value ﬁxed in the LVFRAC-N IC or to a value

determined by the currents ﬂowing into BIAS 1 (U4201-40) or BIAS 2 (U4201-39). The currents are

set by the value of R4251 or R4252 respectively. The selection of the three different bias sources is

done by software programming.

To reduce synthesizer lock time when new frequency data has been loaded into the synthesizer the

magnitude of the loop current is increased by enabling the IADAPT (U4201-45) for a certain

software programmable time (Adapt Mode). The adapt mode timer is started by a low to high

transient of the CSX line. When the synthesizer is within the lock range the current is determined

only by the resistors connected to BIAS 1, BIAS 2, or the internal current source. A settled

synthesizer loop is indicated by a high level of signal LOCK (U4201-4).

The LOCK (U4201-4) signal is routed to one of the µP´s ADCs input U101-56. From the voltage the

µP determines whether LOCK is active. In order to modulate the PLL the two spot modulation

method is utilized. Via pin 10 (MODIN) on U4201 the audio signal is applied to both the A/D

converter (low freq path) as well as the balance attenuator (high freq path). The A/D converter

converts the low frequency analogue modulating signal into a digital code that is applied to the loop

divider, thereby causing the carrier to deviate. The balance attenuator is used to adjust the VCO's

deviation sensitivity to high frequency modulating signals. The output of the balance attenuator is

present at the MODOUT port (U4201-41) and connected to the VCO modulation diode CR4321 via

R4321, C4325.