Pioneer DEH-42 Servicehandleiding - Pagina 16
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@ Pin Functions (UPD63702GF)
[Pin No. [PinName
_[V/O
| FunctionandOperation
Cd
[1
[DVvDD
Cs ~—S_—i Supplies current of positive voltage to thelogiccircuits
|
2 ([RstT
——si'[{t ~—Ssd[ Systemresetinputpin,
Cd
AO
Microcomputer interface
AO="L": STB active and set to address register
AOQ="H": STB active and set to parameter
|
4 |8TB
[1
___| Signal to latch serial data within the LSI
PS
LSCK.C*C'"'CU''L:''UCT_ | Clock input pin to input and output seraldata
Cd
|
—r6 [SO.C™C™C™~*t—C
sé tpt serial data andstatussignal =F ss
C—Ci'"'C;Cid
[CUT {SECUCC*"'dLNESCN'WUN WU Seralataiimputin= =
Cd
Pf
8 TDGNDCUT SCs LogiccircuitGND
[9
[XGND
dL ~—Ssd CrrystaloscillationcircuitGND)
P10 «[XTAL
CdS SC Cs*d Crysttaloscillatorconnectionpin
Cid
Pt
[XTAC
CO
Crystaloscillatorconnectionpin,
Cd
|
12,-« [X.VDD.——sd|~————__s| Supplies current of positive voltage to the crystal oscillation circuit
[13
|DAVDD
| _~—_—_—_—si| Supplies currentof positive voltage tothe D/Aconverter
Cd
ro 14 TR+
~~~ _| Right channel analog audio data output pin
Y=
15 TR-
SY
OO —_| Right channel analog audio data output pin
| 16,17 |DAGND
| ____—si| D/A converter GND
|
18 j{l-
~—~~——Ss([O.—*d Leftchannelanalogaudiodataoutputpin,
Cid
|
19 [te
CS
| __20 |DAVDD
| __—[ Supplies currentof positive
voltagetotheD/Aconverter
i
|
21 [D.VDD
—*Y| ~——sS} Supplies current of positive voltage to logic circuit
ea
ae Flag output pin to indicate that audio data currently being output consists of
noncorrectable data
|
«23.~« | WDCK
|O
| Pin to output double the frequency of LRCK
[Pintooutputtheclock ————"—'"'—'"'"'SCCCC*@d
| _—-24
~+|C16M
|O _| Pin to output the clock
|
25 [EMPH
———«([O__|
Output pin for the pre-emphasis data in the sub-Q code
| __-26 * [DIN
___—s({t_|
Input pin for serial audio data
[27
[DOUT—s—s«d[O
sid OutputpinfortheserialaudiodataCi('C;OC;C;*;C;C'*"*
|
28 |SCKO
—~—«([O__—'| Outputpinfortheclockfortheserialaudiodata
he
ere
i
| Signals to distinguish the right and left channels of the audio data output
from DOUT. Frequency
is 44.1kHz at 50% duty at normal regeneration
Ys 30 :|TX ~~———~—Ss({
O_—_| Output pin for the digital audio interface data
ee
a
Oscillation control pin for high-frequency clock generation VCO used for the
digital PLL u
generation at fast speed of 2- or 4-fold
|
«32, |POUT
———«(|O __| Output point for phase comparison
|
33 [D.GND
«| ~——sd[ GND forthelogiccircuit =
i"'"'"C;C™S™SC*C*C;C*C*C*
| 34 [vco.-——séd{t ~S——sSsd[ Inputpinfortheinverter
—
CC—'*zC
|
35 « |}VCO~—=—F7F)—OMd{O
__| Output pin for the inverter
| =. 36: TD.VDD~—Ss|~S——__—s Supplies current of positive voltage
to the logic circuit
P37 -{PLCK
—Ss«([O
sd Pinformonitoringthebitclock
==
38 | LOCK
Indicates "H" when the synchronized pattern detection signal matches the
frame counter output at the EFM recovery modulation, and "L" when they
don't match
Se eee
(approx. 7.35kHz)
ee
ere
(approx. 7.35kHz)
|
41: |D.GND——«|
~——_—sd[ GND for the logic circuit
| 42,43 [TESTO1
[|
—[Testpins
—i'"'"'C;™S™*S*S™*S™SC™*™C™C™C™C™C™C™C~C~C~C~C™C™C™C~C™CSCSCSC*d
| 44,45 [TM2,1M4
[I _| Pins for controlling regeneration atfastspeed of 2-or4-fold
si
| 46-49 [T4-T7
Sst
Cd Testpins
| 50,51 [C1D1,C1D2_-|O
_| Output pin forindicatingthe Ci errorcorrectionresults
Cd
| 52-54 |C2D1-C2D3_ [0 _| Output pin forindicating the C2 errorcorrectionresults
|
55 |D.VDD
—«|_~——_|
Supplies current of positive voltage to the logic circuit
| ___ 56 |SFSY
_——~—~—«(|O
__| Outputs 1 word of the subcode. Generally, 1 cycle is approx 136 micro seconds
flee
ee
The signal indicates the beginning of the subcode block. The SFSY signal is
output at high level every
98 times
|
_58
|SBSO
~—=+[O
___| Output pin for the subcode data
16