Cypress CY62167EV18 Specificatieblad

Blader online of download pdf Specificatieblad voor {categorie_naam} Cypress CY62167EV18. Cypress CY62167EV18 14 pagina's. Mobl 16 mbit (1m x 16) static ram

Pagina afdrukken
Features
Very high speed: 55 ns
■
Wide voltage range: 1.65V to 2.25V
■
Ultra low standby power
■
Typical standby current: 1.5 μA
❐
Maximum standby current: 12 μA
❐
Ultra low active power
■
Typical active current: 2.2 mA at f = 1 MHz
❐
Easy memory expansion with CE
■
Automatic power down when deselected
■
CMOS for optimum speed and power
■
Offered in Pb-free 48-ball VFBGA packages
■

Functional Description

The CY62167EV18 is a high performance CMOS static RAM
organized as 1M words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL
applications such as cellular telephones. The device also has an
automatic power down feature that reduces power consumption
Logic Block Diagram
Power Down
Circuit
Cypress Semiconductor Corporation
Document #: 38-05447 Rev. *G
, CE
, and OE features
1
2
®
) in portable
DATA IN DRIVERS
A
10
A
9
A
8
A
7
A
1M × 16
6
A
RAM ARRAY
5
A
4
A
3
A
2
A
1
A
0
COLUMN DECODER
CE
2
CE
1
BHE
BLE
•
198 Champion Court
CY62167EV18 MoBL
16 Mbit (1M x 16) Static RAM
by 99 percent when addresses are not toggling. Place the device
into standby mode when deselected (CE
both BHE and BLE are HIGH). The input and output pins (I/O
through I/O
) are placed in a high impedance state when: the
15
device is deselected (CE
HIGH or CE
1
disabled (OE HIGH); both Byte High Enable and Byte Low
Enable are disabled (BHE, BLE HIGH); and a write operation is
in progress (CE
LOW, CE
HIGH and WE LOW).
1
2
To write to the device, take Chip Enables (CE
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
written into the location specified on the address pins (A
A
). If Byte High Enable (BHE) is LOW, then data from I/O pins
19
(I/O
through I/O
) is written into the location specified on the
8
15
address pins (A
through A
0
19
To read from the device, take Chip Enables (CE
HIGH) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins appears
on I/O
to I/O
. If Byte High Enable (BHE) is LOW, then data from
0
7
memory appears on I/O
to I/O
8
9
for a complete description of read and write modes.
For best practice recommendations, refer to the Cypress
application note
AN1064, SRAM System
IO
IO
,
•
San Jose
CA 95134-1709
HIGH or CE
LOW or
1
2
LOW); outputs are
2
LOW and CE
1
through I/O
0
through
0
).
LOW and CE
1
. See the
Truth Table on page
15
Guidelines.
–IO
0
7
–IO
8
15
BHE
WE
CE
2
CE
1
OE
BLE
•
408-943-2600
Revised March 13, 2009
®
0
2
) is
7
2
[+] Feedback