Cypress Semiconductor AutoStore STK14CA8 Specificatieblad - Pagina 2

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Pinouts
Figure 1. 48-Pin SSOP
V
CAP
1
A
2
16
A
3
14
A
4
12
A
5
7
A
6
6
A
7
5
NC
8
A
9
4
NC
10
NC
11
NC
12
V
13
SS
NC
14
NC
15
DQ
16
0
A
17
3
A
18
2
A
19
1
A
20
0
DQ
21
1
DQ
2
22
NC
23
NC
24

Pin Descriptions

Pin Name
I/O
A
-A
Input
16
0
DQ
-DQ
I/O
7
0
E
Input
W
Input
G
Input
V
Power Supply
CC
HSB
I/O
V
Power Supply
CAP
V
Power Supply
SS
NC
No Connect
Note
1. See
Package Diagrams
on page 15 for detailed package size specifications.
Document Number: 001-51592 Rev. **
V
48
CC
A
47
15
46
HSB
45
W
44
A
13
A
43
8
42
A
9
NC
41
40
A
11
39
NC
38
NC
37
NC
36
V
SS
35
NC
34
NC
DQ
33
6
32
G
A
31
10
30
E
29
DQ
7
28
DQ
5
DQ
27
4
DQ
26
3
V
25
CC
Address: The 17 address inputs select one of 131,072 bytes in the nvSRAM array.
Data: Bi-directional 8-bit data bus for accessing the nvSRAM.
Chip Enable: The active low E input selects the device.
Write Enable: The active low W allows to write the data on the DQ pins to the address location
latched by the falling edge of E.
Output Enable: The active low G input enables the data output buffers during read cycles.
De-asserting G high causes the DQ pins to tri-state.
Power: 3.0V, +20%, -10%.
Hardware Store Busy: When low this output indicates a Store is in progress. When pulled low
external to the chip, it initiates a nonvolatile STORE operation. A weak pull up resistor keeps this
pin high if not connected. (Connection is optional).
AutoStore™ Capacitor: Supplies power to nvSRAM during power loss to store data from SRAM to
nonvolatile storage elements.
Ground.
Unlabeled pins have no internal connections.
Figure 2. 32-Pin SOIC
V
CAP
1
A
2
16
3
A
14
A
4
12
A
5
7
A
6
6
A
7
5
A
4
8
A
9
3
A
10
2
A
11
1
A
12
0
DQ
13
0
DQ
14
1
DQ
15
2
V
SS
16
Figure 3. Relative PCB Area Usage
Description
STK14CA8
32
V
CC
31
A
15
30
HSB
29
W
28
A
13
27
A
8
26
A
9
25
A
11
24
G
23
A
10
22
E
21
DQ
7
20
DQ
6
DQ
19
5
18
DQ
4
17
DQ
3
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