Cypress Semiconductor CY7B9911V Specificatieblad

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Features

■

All output pair skew <100 ps typical (250 max)

■

3.75 to 110 MHz output operation

■

User selectable output functions

❐

Selectable skew to 18 ns

❐

Inverted and non-inverted

⁄

❐

Operation at

and

❐

Operation at 2x and 4x input frequency (input as low as

3.75 MHz)

■

Zero input-to-output delay

■

50% duty cycle outputs

■

LVTTL outputs drive 50Ω terminated lines

■

Operates from a single 3.3V supply

■

Low operating current

■

32-pin PLCC package

■

Jitter 100 ps (typical)

Logic Block Diagram

Cypress Semiconductor Corporation

Document Number: 38-07408 Rev. *D

High Speed Low Voltage Programmable Skew

input frequency

TEST

PHASE

FREQ

FILTER

DET

REF

4F0

4F1

SELECT

INPUTS

(THREE

LEVEL)

3F0

3F1

2F0

2F1

1F0

1F1

•

198 Champion Court

Functional Description

The CY7B9911V 3.3V RoboClock+™ High Speed Low

Voltage Programmable Skew Clock Buffer (LVPSCB) offers

user selectable control over system clock functions. These

multiple output clock drivers provide the system integrator with

functions necessary to optimize the timing of high perfor-

mance computer systems. Each of the eight individual drivers,

arranged in four pairs of user controllable outputs, can drive

terminated transmission lines with impedances as low as 50Ω.

They deliver minimal and specified output skews and full swing logic

levels (LVTTL).

Each output is hardwired to one of nine delay or function

configurations. Delay increments of 0.7 to 1.5 ns are deter-

mined by the operating frequency with outputs that can skew

up to ±6 time units from their nominal "zero" skew position. The

completely integrated PLL allows external load and cancels

the transmission line delay effects. When this "zero delay"

capability of the LVPSCB is combined with the selectable

output skew functions, you can create output-to-output delays

of up to ±12 time units.

Divide-by-two and divide-by-four output functions are provided

for additional flexibility in designing complex clock systems.

When combined with the internal PLL, these divide functions

allow distribution of a low frequency clock that are multiplied

by two or four at the clock destination. This facility minimizes

clock distribution difficulty enabling maximum system clock

speed and flexibility.

VCO AND

TIME UNIT

GENERATOR

4Q0

4Q1

SKEW

3Q0

3Q1

SELECT

2Q0

MATRIX

2Q1

1Q0

1Q1

•

San Jose

CA 95134-1709

CY7B9911V

3.3V RoboClock+™

Clock Buffer

•

408-943-2600

Revised June 20, 2007

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