Cypress Semiconductor CY7C1018DV33 Specificatieblad

Blader online of download pdf Specificatieblad voor {categorie_naam} Cypress Semiconductor CY7C1018DV33. Cypress Semiconductor CY7C1018DV33 9 pagina's. 1-mbit (128k x 8) static ram

Cypress Semiconductor CY7C1018DV33 Specificatieblad
Features
• Pin- and function-compatible with CY7C1018CV33
• High speed
— t
= 10 ns
AA
• Low Active Power
— I
= 60 mA @ 10 ns
CC
• Low CMOS Standby Power
— I
= 3 mA
SB2
• 2.0V Data retention
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Center power/ground pinout
• Easy memory expansion with CE and OE options
• Available in Pb-free 32-pin 300-Mil wide Molded SOJ
Logic Block Diagram
INPUTBUFFER
A
0
A
1
A
2
A
3
128K × 8
A
4
ARRAY
A
5
A
6
A
7
A
8
CE
COLUMN
WE
DECODER
OE
Note
1. For guidelines on SRAM system designs, please refer to the 'System Design Guidelines' Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05465 Rev. *D
Functional Description
The CY7C1018DV33 is a high-performance CMOS static
RAM organized as 131,072 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and tri-state drivers. This
device has an automatic power-down feature that significantly
reduces power consumption when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O
specified on the address pins (A
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY7C1018DV33 is available in Pb-free 32-pin 300-Mil
wide Molded SOJ.
POWER
DOWN
198 Champion Court
1-Mbit (128K x 8) Static RAM
[1]
through I/O
) is then written into the location
0
7
Pin Configuration
A
1
0
A
1
2
A
3
2
A
4
3
I/O
0
CE
5
I/O
6
0
I/O
1
I/O
7
1
V
I/O
8
CC
2
V
9
SS
I/O
I/O
10
3
2
I/O
11
3
I/O
WE
4
12
A
4
13
I/O
5
A
5
14
A
15
6
I/O
6
A
16
7
I/O
7
,
San Jose
CA 95134-1709
CY7C1018DV33
through A
).
0
16
through I/O
) are placed in a
0
7
SOJ
Top View
A
32
16
31
A
15
30
A
14
A
29
13
28
OE
27
I/O
7
26
I/O
6
25
V
SS
24
V
CC
23
I/O
5
22
I/O
4
A
21
12
A
20
11
A
19
10
A
18
9
17
A
8
408-943-2600
Revised November 8, 2006
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