Cypress Semiconductor CY7C1338G Specificatieblad - Pagina 17

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Document History Page
Document Title: CY7C1338G 4-Mbit (128K x 32) Flow-Through Sync SRAM
Document Number: 38-05521
REV.
ECN NO.
Issue Date
**
224369
*A
278513
*B
333626
*C
418633
*D
480368
Document #: 38-05521 Rev. *D
Orig. of
Change
See ECN
RKF
New data sheet
See ECN
VBL
Deleted 66 MHz
Changed TQFP to PB-Free TQFP in Ordering Info section
Added PB-Free BG package
See ECN
SYT
Removed 117-MHz speed bin
Modified Address Expansion balls in the pinouts for 100 TQFP and 119 BGA
Packages as per JEDEC standards and updated the Pin Definitions accord-
ingly
Modified V
Replaced 'Snooze' with 'Sleep'
Replaced TBD's for Θ
Resistance table
Removed comment on the availability of BG lead-free package
Updated the Ordering Information by shading and unshading MPNs as per
availability
See ECN
RXU
Converted from Preliminary to Final
Changed address of Cypress Semiconductor Corporation on Page# 1 from
"3901 North First Street" to "198 Champion Court"
Removed I
Modified test condition from V
Modified test condition from V
Modified "Input Load" to "Input Leakage Current except ZZ and MODE" in the
Electrical Characteristics Table
Replaced Package Name column with Package Diagram in the Ordering
Information table
Replaced Package Diagram of 51-85050 from *A to *B
Updated the Ordering Information table
See ECN
VKN
Added the Maximum Rating for Supply Voltage on V
Updated the Ordering Information table.
Description of Change
V
test conditions
OL,
OH
and Θ
to their respective values on the Thermal
JA
JC
from Electrical Characteristics table on Page #8
OS
< V
IH
DD
< V
DDQ
CY7C1338G
< V
to V
IH
DD
to V
< V
DD
DDQ
DD
Relative to GND.
DDQ
Page 17 of 17