Cypress Semiconductor STK11C88 Specificatieblad - Pagina 3
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Device Operation
The STK11C88 is a versatile memory chip that provides several
modes of operation. The STK11C88 can operate as a standard
32K x 8 SRAM. A 32K x 8 array of nonvolatile storage elements
shadow the SRAM. SRAM data can be copied from nonvolatile
memory or nonvolatile data can be recalled to the SRAM.
SRAM Read
The STK11C88 performs a READ cycle whenever CE and OE
are LOW, while WE is HIGH. The address specified on pins
A
determines the 32,768 data bytes accessed. When the
0–14
READ is initiated by an address transition, the outputs are valid
after a delay of t
(READ cycle 1). If the READ is initiated by
AA
CE or OE, the outputs are valid at t
later (READ cycle 2). The data outputs repeatedly respond to
address changes within the t
AA
transitions on any control input pins, and remain valid until
another address change or until CE or OE is brought HIGH.
SRAM Write
A WRITE cycle is performed whenever CE and WE are LOW.
The address inputs must be stable prior to entering the WRITE
cycle and must remain stable until either CE or WE goes HIGH
at the end of the cycle. The data on the common IO pins DQ
are written into the memory if it has valid t
a WE controlled WRITE or before the end of an CE controlled
WRITE. Keep OE HIGH during the entire WRITE cycle to avoid
data bus contention on common IO lines. If OE is left LOW,
internal circuitry turns off the output buffers t
LOW.
Software STORE
Data is transferred from the SRAM to the nonvolatile memory by
a software address sequence. The STK11C88 software STORE
cycle is initiated by executing sequential CE controlled READ
cycles from six specific address locations in exact order. During
the STORE cycle, an erase of the previous nonvolatile data is
first performed, followed by a program of the nonvolatile
elements. When a STORE cycle is initiated, input and output are
disabled until the cycle is completed.
Because a sequence of READs from specific addresses is used
for STORE initiation, it is important that no other READ or WRITE
accesses intervene in the sequence. If they intervene, the
sequence is aborted and no STORE or RECALL takes place.
To initiate the software STORE cycle, the following READ
sequence is performed:
Document Number: 001-50591 Rev. **
or at t
, whichever is
ACE
DOE
access time without the need for
, before the end of
SD
after WE goes
HZWE
1. Read address 0x0E38, Valid READ
2. Read address 0x31C7, Valid READ
3. Read address 0x03E0, Valid READ
4. Read address 0x3C1F, Valid READ
5. Read address 0x303F, Valid READ
6. Read address 0x0FC0, Initiate STORE cycle
The software sequence is clocked with CE controlled READs.
When the sixth address in the sequence is entered, the STORE
cycle commences and the chip is disabled. It is important that
READ cycles and not WRITE cycles are used in the sequence.
It is not necessary that OE is LOW for a valid sequence. After the
t
cycle time is fulfilled, the SRAM is again activated for
STORE
READ and WRITE operation.
Software RECALL
Data is transferred from the nonvolatile memory to the SRAM by
a software address sequence. A software RECALL cycle is
initiated with a sequence of READ operations in a manner similar
to the software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE controlled READ operations is
performed:
1. Read address 0x0E38, Valid READ
2. Read address 0x31C7, Valid READ
0–7
3. Read address 0x03E0, Valid READ
4. Read address 0x3C1F, Valid READ
5. Read address 0x303F, Valid READ
6. Read address 0x0C63, Initiate RECALL cycle
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared, and then the nonvolatile information is transferred into
the SRAM cells. After the t
again ready for READ and WRITE operations. The RECALL
operation does not alter the data in the nonvolatile elements. The
nonvolatile data can be recalled an unlimited number of times.
Hardware RECALL (Power Up)
During power up or after any low power condition (V
an internal RECALL request is latched. When V
exceeds the sense voltage of V
automatically initiated and takes t
If the STK11C88 is in a WRITE state at the end of power up
RECALL, the SRAM data is corrupted. To help avoid this
situation, a 10 Kohm resistor is connected either between WE
and system V
or between CE and system V
CC
STK11C88
cycle time, the SRAM is once
RECALL
<V
CC
once again
CC
, a RECALL cycle is
SWITCH
to complete.
HRECALL
.
CC
Page 3 of 15
),
RESET
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