EG&G ORTEC 442 Bedienings- en onderhoudshandleiding - Pagina 11
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Pagina afdrukken5.5. DISCRIMINATOR
The discriminator permits the 442 to reject all input pulses
that fall below the discriminator level selected, i.e., noise
pulses. The discriminator level can be varied from 0.1 V to
1 V by a front panel potentiometer, R75. If the discrimina
tor level is exceeded by an input pulse and the proper
gating pulses are applied when operating in the gated
mode, a signal is sent to the stretch amplifier, switching
the current in Q23 and Q24 and causing the input pulse to
be stretched.
5.6. STRETCH AMPLIFIER
The stretch amplifier is a noninverting amplifier composed
of transistors Q8-Q25. Q24 is normally conducting, causing
current to flow in D5 and keeping the amplifier loop
closed. When the input pulse exceeds the discriminator
level, the current in Q24 is switched to Q23. The stretch
capacitor, C17, is charged through D5 to the peak voltage
of the input pulse. After the peak voltage occurs, D5 is
back-biased and the peak voltage is stored on C17 until
Q24 is switched on again at the end of the output pulse.
A high-input-impedance noninverting amplifier, Q13-Q18,
acts as a buffer and driver for the voltage on capacitor
C17. This amplifier is included inside the stretch amplifier
loop to provide better l inearity and stability. Q20-Q22
monitors the voltage across D5 and produces a peak detect
signal when D5 transitions to the back-biased condition.
The peak detect pulse is routed to the control logic to
initiate the delay and output width signals.
Potentiometer R18 is provided to adjust the voltage at
TP2 to zero volts when the input voltage to Q8 is zero.
5.7. OUTPUT PULSE DELAY CONTROL
The delay circuit consists of Q48, Q49, and two gates
in ICS. The leading edge of the peak detect signal initiates
the delay circuit, causing it to produce a pulse of width
determined by the setting of R94. The width of the delay
pulse can be varied from 300 nsec to 3 fjsec by varying the
setting of R94. The delay range can be increased by
increasing the value of C32.
5.8. OUTPUT PULSE WIDTH CONTROL
The delay pulse is routed to the output pulse width
control circuit (Q46, Q47, and two gates in IC4). The
trailing edge of the delay pulse energizes the width circuit,
which produces an output pulse from 0.5- to 5-fJsec width,
depending on the setting of R91. The pulse width can be
increased by increasing the value of C30.
5.9. OUTPUT GATE
The stretch amplifier is followed by an output gate
composed of two shunt elements (Q26, Q27) and their
drive circuitry (Q50-Q53). Q26 and Q27 are normally
saturated, shorting the gate of Q28 to ground. The pulse
from the output pulse width control is routed to the base of
Q50, which opens the output gate for a period equal to the
width pulse. This in effect strobes the stretched pulse for a
time equal to the width pulse.
5.10. OUTPUT DRIVER AMPLIFIER
The Output Amplifier is a high-input-impedance, non-
inverting, short-circuit-proof amplifier (Q28-Q40, Q61, 062)
with positive and negative output currents l imited by
039 and Q40 respectively. The front panel output has an
impedance of less than
and the impedance of the rear
panel output is approximately 9312. Potentiometer R52
permits the output dc level to be adjusted from -1.5 V
to -H.5 V.
6. MAINTENANCE
6.1. TESTING PERFORMANCE OF PULSE STRETCHER
The following paragraphs are intended as an aid in the
installation and checkout of the 442. These instructions
present information on waveforms at test points and
output connectors.
Test Equipment The following, or equivalent, test equip
ment is needed. Also, refer to Fig. 5.1 and to schematic
442-0101-SI.
ORTEC 419 Pulse Generator
Tektronix Model 580 Series Oscilloscope
lOOn 8NC Terminators
Vacuum Tube Voltmeter
ORTEC Pulse Shaping Amplifier
Preliminary Procedures
Visually check the module for
possible damage due to shipment and then perform the
following steps: