EG&G ORTEC 476 Gebruiksaanwijzing - Pagina 10
Blader online of download pdf Gebruiksaanwijzing voor {categorie_naam} EG&G ORTEC 476. EG&G ORTEC 476 14 pagina's. Multiplexer/routar
Pagina afdrukken3. A routing signal generator, using 16 input lines and a
4-bit binary decoder; also accommodates any single
channel selection.
4. Routing signal output circuit and analyzer handshake
signals.
5.2.
LINEAR CIRCUIT
Input 1 can be used as the typical circuit. The signal
passes through ONI and Fine Gain adjustment R185 and
is applied to one of the 16 inputs of 101, pin 19. When all
four levels at pins 14 through 17 are high, the input at pin
19 is switched through to pin 28. The linear signal then
passes through A2 and A1 to provide the Linear Out sig
nal through CN17.
Each alternate input circuit is identical to the Input 1 cir
cuit. The selection between the 16 inputs to 101 is a func
tion of the binary-coded levels at its pins 14 through 17,
and this combination is generated by the routing signal
generator.
5.3.
LOGIC GATES
Each of the 16 inputs is also connected to a gated dis
criminator. Input 1 can again be used as the typical circuit.
The input signal from ONI is furnished through 01 to
buffer-shaper 105-8 (the section of 105 that includes pin
8 as the output). The shaped output from 105-8 is fur
nished into discriminator 109-2, where it is compared to
the level furnished from Threshold control R20; when
109-2 triggers, this sets flip-flop 1026-13. 1017-8 provides
a low level to pin 10 of 1016 to indicate that an input has
been acknowledged through channel 0 (the Input 1 in
ternal circuit).
Integrated circuit 1016 encodes the signal from its pin 10
for its 3-line binary output and switches the level at its
pin 15 to high. 1015-8 switches to low to latch the binary
code from 1016 through 1013, where it will remain until
the next input signal initiates a new sequence. The low at
1015-8 also triggers two monostables; 1039-7 turns on the
front panel Busy indicator, and 1039-9 generates an in
hibit to all gates through 1040-3 and IO40-6; no new input
pulse can initiate a response until the gate signal has been
released. The gate signal from 1039-9 is gated through
1040-3 together with the level furnished through the ADO
Busy input circuit, ONI8, and the response through all
channels can thus be inhibited until the ADO Busy returns
to a low level after the signal has been processed.
If the circuits through the rear panel control connectorare
used, the FEO0 line (Front End Oontrol for channel 0)
can be used to aid in determining the exact reset time for
flip-flop 1026-13, or it can be held as a low input to inhibit
any response through channel 0 as a function of the soft
ware in the analyzer.
An input through channel 1 to 7 (0N2 through 0N8) will
generate a logic response through its unique circuit to
trigger its flip-flop within the group from 1026-9 through
1024-7, and the result will be encoded in 1016 for the rout
ing identity to 1013, and the gating will be provided in the
same manner as described above.
An input to channel 8 (0N9) will generate a response
through 1022-13 that is furnished to 1011. When this
occurs, 1011 generates the encoded output through its
pins 6, 7, and 9 and also switches its pins 14 and 15 to high.
The high at 1011-14 causes latch 1013 to look at the inputs
from 1011 instead of those from 1016. The high at 1011-15
carries through 1016 and initiates the responses for
1015-8. An input through channel 9 through 15 (ON10
through 0N16) will generate a logic response through its
unique circuit and trigger its flip-flop within the group
from 1022-9 through IO20-4, and the result will be en
coded in 1011 for the routing identity and control to 1013
in the same manner as described for a signal through
channel 8.
5.4.
ROUTING GENERATOR
A low-true binary code for channels 0 through 15 is pro
vided at pins 15,14,13, and 12, respectively, of 1013. This
information is obtained as described in Section 5.3above.
The channel code is furnished as one of the two input
groups to multiplexer 1014. If 1014-1 is high, this input is
transferred directly to the 4-line output of 1014 and used
as the routing code.
The alternate input to 1014 comes from 1023 and is ac
cepted when 1014-1 is low. 1023 encodes the selection of
switch 317, in which settings 1 through 16 of 817 corre
spond respectively to channels 0 through 15 as decoded
by 10 23.
Switch S18 determines whether 1014-1 is at a high or low
level. When it is set at Normal Multiplex, 1014-1 is high and
the output is the channel code from 1013. When switch
SI8 is set at Single Obannel Select, 1014-1 is low and the
output is the channel code from 1023.
The 4-llne output from 1014 is furnished through inverters
to control the selection by 101 (see Section 5.2). It is also
furnished to four OR gates, 1018-3, -6, -11, and -8, for
transfer as routing output signals. The common control
line to these four gates must be held low to permit the
transfer of the routing code.
5.5. ROUTING OUTPUTS AND HANDSHAKE
SIGNALS
A strobe signal must be furnished from the associated
ADO to complete the transfer of the routing output in
formation. This will be furnished from the ADO in re
sponse to the Linear Out analog signal that has been
furnished through 0N17 (see Section 5.2). Ifasystem has
more than one ADO, the correct SEL line must also have
been pulled to a high level and this information trans
ferred through an internal jumper to pin 9 of 1027-8.
If the 7010/6240B jumper has been set at 6240B, the input
strobe from the analyzer is a low level and will enable the
transfer through the OR gates in 1018. The combination
of FED lines that carry the coded routing signal is deter-